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1. 再颁专利

USRE41464E1 Switching ethernet controller providing packet routing 有权
标题翻译：切换以太网控制器提供数据包路由
公开(公告)号：USRE41464E1
公开(公告)日：2010-07-27
申请号：US10000944
申请日：2001-12-04
申请人： Avigdor Willenz , David Shemla , Yosi Sholt
发明人： Avigdor Willenz , David Shemla , Yosi Sholt
IPC分类号： G06F15/173 , H04L12/28
CPC分类号： H04L49/25 , H04L49/201 , H04L49/254 , H04L49/351
摘要： A switched Ethernet controller (SEC) device and associated method that provides processor based intervention in the packet routing decision process is provided. The method of routing a multicast packet between a source port on a source device and a plurality of destination ports on a plurality of destination devices, utilizes a processor. The method includes the steps of the source device receiving the multicast packet via the source port, the source device sending the multicast packet to the processor, the processor examining the multicast packet, the processor determining the plurality of destination devices and corresponding the plurality of destination ports based on the results obtained during the step of examining, the processor transferring the multicast packet to the plurality of destination devices, and the plurality of destination devices sending the multicast packet to the plurality of destination ports.
摘要翻译：提供了一种在分组路由决策过程中提供基于处理器的干预的交换以太网控制器（SEC）设备和相关联的方法。在源设备上的源端口与多个目的地设备上的多个目的地端口之间路由组播分组的方法利用处理器。该方法包括以下步骤：源设备经由源端口接收组播报文，源设备向处理器发送组播报文，处理器检查组播报文，处理器确定多个目标设备，并对应多个目的地基于在检查步骤中获得的结果，处理器将多播分组传送到多个目的地设备，以及将多播分组发送到多个目的地端口的多个目的地设备。

2. 发明授权

US5553268A Memory operations priority scheme for microprocessors 失效
标题翻译：微处理器的存储器操作优先级方案
公开(公告)号：US5553268A
公开(公告)日：1996-09-03
申请号：US715294
申请日：1991-06-14
申请人： Avigdor Willenz , Philip Bourekas , Yehayahu Mor
发明人： Avigdor Willenz , Philip Bourekas , Yehayahu Mor
IPC分类号： G06F13/18 , G06F13/28
CPC分类号： G06F13/28 , G06F13/18
摘要： A structure and a method are provided to implement a memory bus arbiter, in which separate priorities are provided to instruction and data reads from the main memory. In one embodiment in a microprocessor with an on-chip cache, the present invention provides an arbiter which yields the memory bus, in decreasing priority order, to an ongoing bus transaction, a "direct memory access" (DMA) request, an instruction read resulting from a cache miss, a pending write request, and a read request, including reference to an uncacheable portion of memory and a data cache miss.
摘要翻译：提供了一种实现存储器总线仲裁器的结构和方法，其中提供了从主存储器读取指令和数据的单独优先级。在具有片上高速缓存的微处理器的一个实施例中，本发明提供了一种仲裁器，其以降低的优先级顺序产生存储器总线到正在进行的总线事务，“直接存储器访问”（DMA）请求，读取指令由高速缓存未命中，挂起的写请求和读请求引起，包括引用存储器的不可缓存部分和数据高速缓存未命中。

3. 发明授权

US5894176A Flexible reset scheme supporting normal system operation, test and emulation modes 失效
标题翻译：灵活的复位方案支持正常的系统运行，测试和仿真模式
公开(公告)号：US5894176A
公开(公告)日：1999-04-13
申请号：US238192
申请日：1994-05-04
申请人： Philip A. Bourekas , Avigdor Willenz , Yeshayahu Mor
发明人： Philip A. Bourekas , Avigdor Willenz , Yeshayahu Mor
IPC分类号： G01R31/317 , H03K3/02
CPC分类号： G01R31/31701
摘要： A structure and a method are provided to implement a reset scheme for an integrated circuit supporting a variety of testing and debugging equipment. The control and I/O pins of the integrated circuit are each set to a high impedance state when the signals of a reset pin and a mode pin are both asserted. If the signal on the mode pin remains asserted at the time the signal on the reset pin is negated, the control and I/O pins of the integrated circuit remain in the high impedance state until the next time the signal on the reset pin is asserted. Otherwise, the control and I/O pins of the integrated circuits are enabled upon negation of the signal on the reset pin. In one embodiment, the mode pin is multiplexed with an pin used for receiving interrupt signals during functional operation.
摘要翻译：提供了一种结构和方法来实现支持各种测试和调试设备的集成电路的复位方案。当复位引脚和模式引脚的信号都被断言时，集成电路的控制和I / O引脚都被设置为高阻抗状态。如果在复位引脚上的信号被否定时，模式引脚上的信号保持有效，则集成电路的控制和I / O引脚将保持在高阻态，直到下一次复位引脚上的信号被置为有效。否则，当复位引脚上的信号无效时，集成电路的控制和I / O引脚被使能。在一个实施例中，模式引脚与用于在功能操作期间接收中断信号的引脚复用。

4. 发明授权

US5809557A Memory array comprised of multiple FIFO devices 失效
标题翻译：由多个FIFO器件组成的存储器阵列
公开(公告)号：US5809557A
公开(公告)日：1998-09-15
申请号：US790153
申请日：1997-01-28
申请人： David Shemla , Avigdor Willenz , Gerardo Waisbaum
发明人： David Shemla , Avigdor Willenz , Gerardo Waisbaum
IPC分类号： G06F5/06 , G06F12/06
CPC分类号： G06F5/065
摘要： A multiple FIFO array which does not use numerous single FIFO devices is provided. The multiple FIFO array includes a memory partitioned into a plurality of N sections, each section corresponding to one of N FIFOs. The memory has a write address input, write strobe input, data input, read address input, read strobe and data output. Also included is a plurality of N write pointer registers, a write multiplexer having N write inputs, a write output and a write select input, a plurality of N read registers and a read multiplexer. Each write pointer register corresponds to one of N FIFOs and each write pointer register holds the write address corresponding to one of N FIFOs. The N write inputs of the write multiplexer are coupled to the output of the plurality of N write pointer registers, the write output is coupled to the write address input in the memory and the write select input couples one of the N write inputs to the write output. Each read pointer register corresponds to one of the N FIFOs, each read pointer register holding the read address corresponding to one of the N FIFOs. The read multiplexer has N read inputs, a read output and a read select input, the N read inputs being coupled to the output of the plurality of N read pointer registers, the read output coupled to the read address input in the memory, and the read select input coupling one of the N read inputs to the read output.
摘要翻译：提供了不使用大量单个FIFO设备的多FIFO阵列。多FIFO阵列包括划分成多个N个部分的存储器，每个部分对应于N个FIFO之一。存储器具有写地址输入，写选通输入，数据输入，读地址输入，读选通和数据输出。还包括多个N个写入指针寄存器，具有N个写入输入的写入多路复用器，写入输出和写入选择输入，多个N个读取寄存器和读取多路复用器。每个写指针寄存器对应于N个FIFO之一，并且每个写指针寄存器保持对应于N个FIFO之一的写地址。写入多路复用器的N个写入输入耦合到多个N个写入指针寄存器的输出，写入输出耦合到存储器中输入的写入地址，并且写入选择输入将N个写入输入之一耦合到写入输出。每个读指针寄存器对应于N个FIFO之一，每个读指针寄存器保持对应于N个FIFO之一的读地址。读取多路复用器具有N个读取输入，读取输出和读取选择输入，N个读取输入耦合到多个N个读取指针寄存器的输出，耦合到在存储器中输入的读取地址的读取输出，以及读取选择输入将N个读取输入之一耦合到读取输出。

5. 发明授权

US5517659A Multiplexed status and diagnostic pins in a microprocessor with on-chip caches 失效
标题翻译：具有片内缓存的微处理器中的多路复用状态和诊断引脚
公开(公告)号：US5517659A
公开(公告)日：1996-05-14
申请号：US240958
申请日：1994-05-11
申请人： Philip A. Bourekas , Yeshayahu Mor , Scott Revak , Avigdor Willenz
发明人： Philip A. Bourekas , Yeshayahu Mor , Scott Revak , Avigdor Willenz
IPC分类号： G06F11/28 , G06F11/00 , G06F11/26 , G06F11/267 , G06F11/34 , G06F12/08 , G06F15/78 , G06F15/00
CPC分类号： G06F11/261 , G06F11/2236 , G06F11/349 , G06F2201/885
摘要： In a microprocessor, two output pins are dedicated to providing information to assist in diagnosing problems relating to internal instruction and data caches or the software executing in the caches. The information on the pins is time-multiplexed. In a first phase, the pins indicate whether the data or instruction cache is accessed and whether a cache miss has occurred. In a second phase, the pins carry signals identifying the address reference which resulted in a cache miss.
摘要翻译：在微处理器中，两个输出引脚专用于提供信息以帮助诊断与内部指令和数据高速缓存相关的问题或在高速缓存中执行的软件。引脚上的信息被时分复用。在第一阶段中，引脚指示数据或指令高速缓存是否被访问以及是否发生了高速缓存未命中。在第二阶段，引脚携带识别导致高速缓存未命中的地址引用的信号。

6. 再颁专利

USRE43058E1 Switching ethernet controller 有权
标题翻译：切换以太网控制器
公开(公告)号：USRE43058E1
公开(公告)日：2012-01-03
申请号：US11469807
申请日：2006-09-01
申请人： David Shemla , Avigdor Willenz
发明人： David Shemla , Avigdor Willenz
IPC分类号： H04L12/28 , H04L12/56
摘要： An Ethernet controller, for use within an Ethernet network of other Ethernet controller connected together by a bus, is provided. The Ethernet controller includes a plurality of ports including at least one bus port associated with ports connected to other switching Ethernet controllers, a hash table for storing addresses of ports within the Ethernet network, a hash table address control, a storage buffer including a multiplicity of contiguous buffers in which to temporarily store said packet, an empty list including a multiplicity of single bit buffers, a packet storage manager, a packet transfer manager and a write-only bus communication unit. The hash table address control hashes the address of a packet to initial hash table location values, changes the hash table location values by a fixed jump amount if the address values stored in the initial hash table location do not match the received address, and provides at least an output port number of the port associated with the received address. The packet storage manager associates the state of the bit of a single bit buffer with the empty or full state of an associated contiguous buffer and generates the address of a contiguous buffer. The packet transfer manager directs the temporarily stored packet to the port determined by said hash table control unit. The write-only bus communication unit is activated by the packet transfer manager, for transferring the packet out of the bus port by utilizing the bus for write only operations.
摘要翻译：提供了一种以太网控制器，用于通过总线连接在一起的其他以太网控制器的以太网网络内。以太网控制器包括多个端口，其包括与连接到其他交换以太网控制器的端口相关联的至少一个总线端口，用于存储以太网内的端口的地址的散列表，散列表地址控制，包括多个临时存储所述分组的连续缓冲器，包括多个单个位缓冲器的空列表，分组存储管理器，分组传送管理器和只写总线通信单元。哈希表地址控制将数据包的地址散列到初始哈希表位置值，如果存储在初始哈希表位置的地址值与接收到的地址不匹配，则将哈希表位置值更改为固定跳转量，并提供至少与接收到的地址相关联的端口的输出端口号。分组存储管理器将单个位缓冲器的位的状态与相关联的连续缓冲器的空或完全状态相关联，并且生成连续缓冲器的地址。分组传送管理器将临时存储的分组引导到由所述散列表控制单元确定的端口。只写总线通信单元被分组传送管理器激活，用于通过利用用于仅写操作的总线将数据包传出总线端口。

7. 再颁专利

USRE39514E1 Switching ethernet controller 有权
标题翻译：切换以太网控制器
公开(公告)号：USRE39514E1
公开(公告)日：2007-03-13
申请号：US10872147
申请日：2004-06-21
申请人： David Shemla , Avigdor Willenz
发明人： David Shemla , Avigdor Willenz
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/254 , H04L49/201 , H04L49/3009 , H04L49/3018 , H04L49/351
摘要： An Ethernet controller, for use within an Ethernet network of other Ethernet controller connected together by a bus, is provided. The Ethernet controller includes a plurality of ports including at least one bus port associated with ports connected to other switching Ethernet controllers, a hash table for storing addresses of ports within the Ethernet network, a hash table address control, a storage buffer including a multiplicity of contiguous buffers in which to temporarily store said packet, an empty list including a multiplicity of single bit buffers, a packet storage manager, a packet transfer manager and a write-only bus communication unit. The hash table address control hashes the address of a packet to initial hash table location values, changes the hash table location values by a fixed jump amount if the address values stored in the initial hash table location do not match the received address, and provides at least an output port number of the port associated with the received address. The packet storage manager associates the state of the bit of a single bit buffer with the empty or full state of an associated contiguous buffer and generates the address of a contiguous buffer. The packet transfer manager directs the temporarily stored packet to the port determined by said hash table control unit. The write-only bus communication unit is activated by the packet transfer manager, for transferring the packet out of the bus port by utilizing the bus for write only operations.
摘要翻译：提供了一种以太网控制器，用于通过总线连接在一起的其他以太网控制器的以太网网络内。以太网控制器包括多个端口，其包括与连接到其他交换以太网控制器的端口相关联的至少一个总线端口，用于存储以太网内的端口的地址的散列表，散列表地址控制，包括多个临时存储所述分组的连续缓冲器，包括多个单个位缓冲器的空列表，分组存储管理器，分组传送管理器和只写总线通信单元。哈希表地址控制将数据包的地址散列到初始哈希表位置值，如果存储在初始哈希表位置的地址值与接收到的地址不匹配，则将哈希表位置值更改为固定跳转量，并提供至少与接收到的地址相关联的端口的输出端口号。分组存储管理器将单个位缓冲器的位的状态与相关联的连续缓冲器的空或完全状态相关联，并且生成连续缓冲器的地址。分组传送管理器将临时存储的分组引导到由所述哈希表控制单元确定的端口。只写总线通信单元被分组传送管理器激活，用于通过利用用于仅写操作的总线将数据包传出总线端口。

8. 发明授权

US5590310A Method and structure for data integrity in a multiple level cache system 失效
标题翻译：多级缓存系统中数据完整性的方法和结构
公开(公告)号：US5590310A
公开(公告)日：1996-12-31
申请号：US426440
申请日：1995-04-21
申请人： Avigdor Willenz , Yiftach Tzori
发明人： Avigdor Willenz , Yiftach Tzori
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831
摘要： A structure and a method provide data integrity for a multiprocessor system having a cache memory and a snoop tag cache. In one embodiment, the snoop tag cache copies the tags of a primary cache. Whenever a write operation occurs, the snoop tag cache is accessed to determine if the accessed tag matches a predetermined portion of the address of the memory location on which the write operation is performed. If so, a signal is sent to the CPU associated with the primary cache so that the corresponding entries in the primary cache and the snoop tag cache can be invalidated.
摘要翻译：结构和方法为具有高速缓冲存储器和窥探标签高速缓存的多处理器系统提供数据完整性。在一个实施例中，窥探标签缓存复制主缓存的标签。每当写入操作发生时，访问窥探标签高速缓存以确定所访问的标签是否与执行写入操作的存储器位置的地址的预定部分匹配。如果是这样，则将信号发送到与主缓存相关联的CPU，使得主缓存和窥探标签高速缓存中的相应条目可以被无效。

9. 发明授权

US5398211A Structure and method for providing prioritized arbitration in a dual port memory 失效
标题翻译：在双端口存储器中提供优先仲裁的结构和方法
公开(公告)号：US5398211A
公开(公告)日：1995-03-14
申请号：US136781
申请日：1993-10-14
申请人： Avigdor Willenz , Kelly A. Maas
发明人： Avigdor Willenz , Kelly A. Maas
IPC分类号： G11C8/16 , G11C8/00
CPC分类号： G11C8/16
摘要： An integrated circuit dual port memory provides a preferred port which is always granted priority of memory access when memory access requests arrive simultaneous from both ports of the dual port memory. To implement this priority scheme, the memory request signal from the preferred port controls a multiplexor to select the input signals from the preferred port over the input signals from the non-preferred port. The memory request signal from the preferred port also serves as a busy signal to block a simultaneous memory access by the non-preferred port. In one embodiment, memory request signals of both ports are latched into registers clocked by the same clock signal.
摘要翻译：集成电路双端口存储器提供优选端口，当存储器访问请求从双端口存储器的两个端口同时到达时，该端口始终被授予存储器访问的优先级。为了实现该优先方案，来自优选端口的存储器请求信号控制多路复用器，以通过来自非优选端口的输入信号从优选端口选择输入信号。来自优选端口的存储器请求信号也用作忙信号，以阻止非首选端口的同时存储器访问。在一个实施例中，两个端口的存储器请求信号被锁存到由相同时钟信号计时的寄存器中。

10. 发明授权

US5386579A Minimum pin-count multiplexed address/data bus with byte enable and burst address counter support microprocessor transmitting byte enable signals on multiplexed address/data bus having burst address counter for supporting signal datum and burst transfer 失效
标题翻译：具有字节使能和突发地址计数器的最小引脚数复用地址/数据总线支持微处理器在多路复用地址/数据总线上发送字节使能信号，具有用于支持信号数据和突发传输的突发地址计数器
公开(公告)号：US5386579A
公开(公告)日：1995-01-31
申请号：US760794
申请日：1991-09-16
申请人： Philip A. Bourekas , Avigdor Willenz , Yeshayahu Mor , Danh LeNgoc , Scott Revak
发明人： Philip A. Bourekas , Avigdor Willenz , Yeshayahu Mor , Danh LeNgoc , Scott Revak
IPC分类号： G06F12/08 , G06F13/28 , G06F12/00 , G06F15/76
CPC分类号： G06F13/287 , G06F12/0879
摘要： A multiplexed address and data bus system provides a minimum pin count with byte enable and burst address counter support. The partitioning of the address bus includes separate byte enables to indicate specifically which bytes of the word are being accessed, and two independent address lines which can function as a counter to support the burst refill. Both block reads or single datum transfers are handled similarly: a single addressing phase with multiple data phases; and all addresses in the memory system; are derived directly from the same pins regardless of whether it is a block read or not. The system allows for low cost packaging while maintaining a variety of system capabilities.
摘要翻译：多路复用的地址和数据总线系统提供了一个最小的引脚数，具有字节使能和突发地址计数器支持地址总线的划分包括单独的字节使能，可以具体指出正在访问字的哪些字节，以及两个独立的地址线，它们可用作计数器以支持突发补充。块读取或单个数据传输都类似地处理：具有多个数据阶段的单个寻址阶段; 和内存系统中的所有地址; 直接来自相同的引脚，而不管它是否读取块。该系统允许低成本的包装，同时保持各种系统功能。

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