专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 再颁专利

USRE43058E1 Switching ethernet controller 有权
标题翻译：切换以太网控制器
公开(公告)号：USRE43058E1
公开(公告)日：2012-01-03
申请号：US11469807
申请日：2006-09-01
申请人： David Shemla , Avigdor Willenz
发明人： David Shemla , Avigdor Willenz
IPC分类号： H04L12/28 , H04L12/56
摘要： An Ethernet controller, for use within an Ethernet network of other Ethernet controller connected together by a bus, is provided. The Ethernet controller includes a plurality of ports including at least one bus port associated with ports connected to other switching Ethernet controllers, a hash table for storing addresses of ports within the Ethernet network, a hash table address control, a storage buffer including a multiplicity of contiguous buffers in which to temporarily store said packet, an empty list including a multiplicity of single bit buffers, a packet storage manager, a packet transfer manager and a write-only bus communication unit. The hash table address control hashes the address of a packet to initial hash table location values, changes the hash table location values by a fixed jump amount if the address values stored in the initial hash table location do not match the received address, and provides at least an output port number of the port associated with the received address. The packet storage manager associates the state of the bit of a single bit buffer with the empty or full state of an associated contiguous buffer and generates the address of a contiguous buffer. The packet transfer manager directs the temporarily stored packet to the port determined by said hash table control unit. The write-only bus communication unit is activated by the packet transfer manager, for transferring the packet out of the bus port by utilizing the bus for write only operations.
摘要翻译：提供了一种以太网控制器，用于通过总线连接在一起的其他以太网控制器的以太网网络内。以太网控制器包括多个端口，其包括与连接到其他交换以太网控制器的端口相关联的至少一个总线端口，用于存储以太网内的端口的地址的散列表，散列表地址控制，包括多个临时存储所述分组的连续缓冲器，包括多个单个位缓冲器的空列表，分组存储管理器，分组传送管理器和只写总线通信单元。哈希表地址控制将数据包的地址散列到初始哈希表位置值，如果存储在初始哈希表位置的地址值与接收到的地址不匹配，则将哈希表位置值更改为固定跳转量，并提供至少与接收到的地址相关联的端口的输出端口号。分组存储管理器将单个位缓冲器的位的状态与相关联的连续缓冲器的空或完全状态相关联，并且生成连续缓冲器的地址。分组传送管理器将临时存储的分组引导到由所述散列表控制单元确定的端口。只写总线通信单元被分组传送管理器激活，用于通过利用用于仅写操作的总线将数据包传出总线端口。

2. 再颁专利

USRE39514E1 Switching ethernet controller 有权
标题翻译：切换以太网控制器
公开(公告)号：USRE39514E1
公开(公告)日：2007-03-13
申请号：US10872147
申请日：2004-06-21
申请人： David Shemla , Avigdor Willenz
发明人： David Shemla , Avigdor Willenz
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/254 , H04L49/201 , H04L49/3009 , H04L49/3018 , H04L49/351
摘要： An Ethernet controller, for use within an Ethernet network of other Ethernet controller connected together by a bus, is provided. The Ethernet controller includes a plurality of ports including at least one bus port associated with ports connected to other switching Ethernet controllers, a hash table for storing addresses of ports within the Ethernet network, a hash table address control, a storage buffer including a multiplicity of contiguous buffers in which to temporarily store said packet, an empty list including a multiplicity of single bit buffers, a packet storage manager, a packet transfer manager and a write-only bus communication unit. The hash table address control hashes the address of a packet to initial hash table location values, changes the hash table location values by a fixed jump amount if the address values stored in the initial hash table location do not match the received address, and provides at least an output port number of the port associated with the received address. The packet storage manager associates the state of the bit of a single bit buffer with the empty or full state of an associated contiguous buffer and generates the address of a contiguous buffer. The packet transfer manager directs the temporarily stored packet to the port determined by said hash table control unit. The write-only bus communication unit is activated by the packet transfer manager, for transferring the packet out of the bus port by utilizing the bus for write only operations.
摘要翻译：提供了一种以太网控制器，用于通过总线连接在一起的其他以太网控制器的以太网网络内。以太网控制器包括多个端口，其包括与连接到其他交换以太网控制器的端口相关联的至少一个总线端口，用于存储以太网内的端口的地址的散列表，散列表地址控制，包括多个临时存储所述分组的连续缓冲器，包括多个单个位缓冲器的空列表，分组存储管理器，分组传送管理器和只写总线通信单元。哈希表地址控制将数据包的地址散列到初始哈希表位置值，如果存储在初始哈希表位置的地址值与接收到的地址不匹配，则将哈希表位置值更改为固定跳转量，并提供至少与接收到的地址相关联的端口的输出端口号。分组存储管理器将单个位缓冲器的位的状态与相关联的连续缓冲器的空或完全状态相关联，并且生成连续缓冲器的地址。分组传送管理器将临时存储的分组引导到由所述哈希表控制单元确定的端口。只写总线通信单元被分组传送管理器激活，用于通过利用用于仅写操作的总线将数据包传出总线端口。

3. 发明授权

US06941392B2 Buffer switch having descriptor cache and method thereof 失效
标题翻译：具有描述符缓存的缓冲器开关及其方法
公开(公告)号：US06941392B2
公开(公告)日：2005-09-06
申请号：US10835270
申请日：2004-04-28
申请人： David Shemla , Rami Rozensvaig
发明人： David Shemla , Rami Rozensvaig
IPC分类号： H04L12/861 , H04L12/879 , H04L12/935 , G06F13/00
CPC分类号： H04L49/901 , H04L49/3036 , H04L49/90
摘要： A buffer switch comprises a data memory that stores a plurality of data. A cache memory comprises a plurality of FIFO mini-queues each storing a plurality of descriptors each corresponding to a respective one of the plurality of data. An output memory comprises a plurality of output queues. A burst writer simultaneously transfers M ones of the plurality of descriptors stored in a corresponding one of the plurality of mini-queues to at least a corresponding one of the plurality of output queues. The burst writer accesses the output memory, when the output memory is available, once for every M ones of the plurality of descriptors.
摘要翻译：缓冲器开关包括存储多个数据的数据存储器。高速缓冲存储器包括多个FIFO微型队列，每个FIFO小型队列存储多个描述符，每个描述符对应于多个数据中的相应一个。输出存储器包括多个输出队列。突发写入器将存储在多个微型队列中的相应一个的多个描述符中的M个一起传送到多个输出队列中的至少一个相应的一个输出队列。当输出存储器可用时，突发写入器访问输出存储器，对于多个描述符中的每个M个存储器一次。

4. 发明授权

US06601116B1 Network switch having descriptor cache and method thereof 有权
标题翻译：具有描述符缓存的网络交换机及其方法
公开(公告)号：US06601116B1
公开(公告)日：2003-07-29
申请号：US09360980
申请日：1999-07-26
申请人： David Shemla , Rami Rozensvaig
发明人： David Shemla , Rami Rozensvaig
IPC分类号： G06F1300
CPC分类号： H04L49/901 , H04L49/3036 , H04L49/90
摘要： A device for writing descriptors, the device including a local memory comprising a multiplicity of mini-queues, wherein each of the mini-queues temporarily stores a plurality of descriptors, wherein each of the descriptors is associated with one of the data packets. Additionally including an output memory comprising a multiplicity of output queues, wherein each of the output queues in output memory is associated with one of the queues in said local memory, and a burst writer which writes N descriptors simultaneously from the mini-queue in the local memory to its associated output queue in output memory.
摘要翻译：一种用于写入描述符的设备，所述设备包括包括多个小型队列的本地存储器，其中每个所述小型队列临时存储多个描述符，其中每个描述符与所述数据分组之一相关联。另外包括包括多个输出队列的输出存储器，其中输出存储器中的每个输出队列与所述本地存储器中的一个队列相关联，以及突发写入器，其从本地的小型队列同时写入N个描述符内存到输出内存中的相关输出队列。

5. 发明授权

US5913042A Method and apparatus for managing packet memory 失效
标题翻译：用于管理数据包存储器的方法和装置
公开(公告)号：US5913042A
公开(公告)日：1999-06-15
申请号：US779063
申请日：1997-01-07
申请人： David Shemla , Yosi Sholt
发明人： David Shemla , Yosi Sholt
IPC分类号： G06F15/173 , H04L12/861 , H04L12/879 , H04L12/883 , H04L12/931 , H04L12/933 , G06F15/16 , H04L12/54
CPC分类号： H04L49/9057 , G06F15/17375 , H04L49/103 , H04L49/90 , H04L49/9021 , H04L49/9026 , H04L49/9047 , H04L49/201
摘要： A method and apparatus for managing packet memory is provided The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.
摘要翻译：提供了一种用于管理分组存储器的方法和装置。该装置包括空列表，存储缓冲器和用于更新存储缓冲器和空列表的装置。空列表包括多个单个位缓冲区。存储缓冲器包括多个连续缓冲器，其中每个单个位缓冲器与一个连续缓冲器相关联。单个位缓冲器的位的状态指示相关连续缓冲器的空或完全状态，连续缓冲器的地址是其相关联的单位缓冲器的地址或编号的简单函数。更新装置将数据存储在相邻缓冲器中并从其中移除数据，并相应地更新相关联的单个位缓冲器的状态。

6. 发明申请

US20090296717A1 VLAN PROTOCOL 有权
标题翻译： VLAN协议
公开(公告)号：US20090296717A1
公开(公告)日：2009-12-03
申请号：US12539168
申请日：2009-08-11
申请人： Eitan Medina , David Shemla
发明人： Eitan Medina , David Shemla
IPC分类号： H04L12/56
CPC分类号： H04L29/12801 , H04L12/4641 , H04L12/467 , H04L29/12839 , H04L45/745 , H04L61/6004 , H04L61/6022
摘要： A switch controller includes a plurality of ports, a hash table, and a hash table control unit. The plurality of ports includes at least one bus port associated with ports connected to other switch controllers. The hash table stores MAC addresses and VLAN ids of ports within a network. The hash table control unit hashes a MAC address and a VLAN id of a packet to a first hash table location.
摘要翻译：开关控制器包括多个端口，散列表和散列表控制单元。多个端口包括与连接到其他交换机控制器的端口相关联的至少一个总线端口。哈希表存储网络中端口的MAC地址和VLAN ID。散列表控制单元将分组的MAC地址和VLAN id分别散列到第一散列表位置。

7. 发明授权

US07573882B2 VLAN protocol 有权
标题翻译： VLAN协议
公开(公告)号：US07573882B2
公开(公告)日：2009-08-11
申请号：US11243710
申请日：2005-10-05
申请人： Eitan Medina , David Shemla
发明人： Eitan Medina , David Shemla
IPC分类号： H04L12/28 , H04L12/56 , H04L1/00 , H04L12/26 , G06F15/173
CPC分类号： H04L29/12801 , H04L12/4641 , H04L12/467 , H04L29/12839 , H04L45/745 , H04L61/6004 , H04L61/6022
摘要： A generally full-wire throughput, switching Ethernet controller used within an Ethernet network of other switching Ethernet controllers connected together by a bus. The controller comprises a plurality of ports including at least one bus port associated with ports connected to other switching Ethernet controllers. A hash table stores MAC addresses and VLAN ids of ports within said Ethernet network. A hash table address control hashes the MAC address and VLAN id of a packet to initial hash table location values, changes the hash table location values by a fixed jump amount if the address and VLAN id values stored in said initial hash table location do not match the received address and VLAN id, and provides at least an output port number of the port associated with the received address and VLAN id. A storage buffer includes a multiplicity of contiguous buffers in which to temporarily store said packet.
摘要翻译：通用全线吞吐量，交换以太网控制器，用于通过总线连接在一起的其他交换以太网控制器的以太网中。控制器包括多个端口，其包括与连接到其他交换以太网控制器的端口相关联的至少一个总线端口。哈希表存储所述以太网内的端口的MAC地址和VLAN ID。散列表地址控制将数据包的MAC地址和VLAN ID分配到初始哈希表位置值，如果存储在所述初始哈希表位置中的地址和VLAN ID值不匹配，则将哈希表位置值更改固定跳转量接收到的地址和VLAN ID，并至少提供与接收到的地址和VLAN ID相关联的端口的输出端口号。存储缓冲器包括多个连续缓冲器，其中临时存储所述分组。

8. 发明授权

US06829245B1 Head of line blocking 有权
标题翻译：线阻塞
公开(公告)号：US06829245B1
公开(公告)日：2004-12-07
申请号：US09348351
申请日：1999-07-08
申请人： Eitan Medina , David Shemla , Yosef Solt
发明人： Eitan Medina , David Shemla , Yosef Solt
IPC分类号： H04L1256
CPC分类号： H04L49/508 , H04L49/201 , H04L49/30 , H04L49/501
摘要： A network switch which includes a plurality of output ports, at least one input port and a queuing manager. Each output port has a control unit associated therewith. The input port receives incoming data destined for various ones of the output ports. The queuing manager directs the incoming data to their destination output ports. Each control unit includes an output queue, a fullness/emptiness sensor and a head of line (HOL) mask. The output queue stores the incoming data destined for its associated output port. The sensor senses when the output queue reaches a fullness or an emptiness state. The HOL mask is connected to the output of the sensor and blocks inflow of the incoming data to the output queue when the sensor senses the fullness state and for enabling inflow when the sensor senses the emptiness state.
摘要翻译：一种网络交换机，包括多个输出端口，至少一个输入端口和排队管理器。每个输出端口具有与其相关联的控制单元。输入端口接收去往各种输出端口的输入数据。排队管理器将传入的数据引导到其目标输出端口。每个控制单元包括输出队列，丰满度/空虚传感器和行头（HOL）掩模。输出队列存储发往其相关输出端口的输入数据。传感器检测输出队列何时达到饱和或空虚状态。当传感器感测到充满状态并且当传感器感测到空虚状态时，HOL掩模连接到传感器的输出并阻止输入数据流入输出队列。

9. 发明授权

US06240065B1 Bit clearing mechanism for an empty list 失效
标题翻译：位清空机制为空列表
公开(公告)号：US06240065B1
公开(公告)日：2001-05-29
申请号：US09129444
申请日：1998-07-30
申请人： Eitan Medina , Rami Rozenzveig , David Shemla
发明人： Eitan Medina , Rami Rozenzveig , David Shemla
IPC分类号： G06F1516
CPC分类号： H04L49/103 , G06F15/17375 , H04L49/201 , H04L49/30 , H04L49/501 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9047
摘要： A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.
摘要翻译：提供了一种用于管理分组存储器的方法和装置。该装置包括空列表，存储缓冲器和用于更新存储缓冲器和空列表的装置。空列表包括多个单个位缓冲区。存储缓冲器包括多个连续缓冲器，其中每个单个位缓冲器与一个连续缓冲器相关联。单个位缓冲器的位的状态指示相关连续缓冲器的空或完全状态，连续缓冲器的地址是其相关联的单位缓冲器的地址或编号的简单函数。更新装置将数据存储在相邻缓冲器中并从其中移除数据，并相应地更新相关联的单个位缓冲器的状态。

10. 发明授权

US5809557A Memory array comprised of multiple FIFO devices 失效
标题翻译：由多个FIFO器件组成的存储器阵列
公开(公告)号：US5809557A
公开(公告)日：1998-09-15
申请号：US790153
申请日：1997-01-28
申请人： David Shemla , Avigdor Willenz , Gerardo Waisbaum
发明人： David Shemla , Avigdor Willenz , Gerardo Waisbaum
IPC分类号： G06F5/06 , G06F12/06
CPC分类号： G06F5/065
摘要： A multiple FIFO array which does not use numerous single FIFO devices is provided. The multiple FIFO array includes a memory partitioned into a plurality of N sections, each section corresponding to one of N FIFOs. The memory has a write address input, write strobe input, data input, read address input, read strobe and data output. Also included is a plurality of N write pointer registers, a write multiplexer having N write inputs, a write output and a write select input, a plurality of N read registers and a read multiplexer. Each write pointer register corresponds to one of N FIFOs and each write pointer register holds the write address corresponding to one of N FIFOs. The N write inputs of the write multiplexer are coupled to the output of the plurality of N write pointer registers, the write output is coupled to the write address input in the memory and the write select input couples one of the N write inputs to the write output. Each read pointer register corresponds to one of the N FIFOs, each read pointer register holding the read address corresponding to one of the N FIFOs. The read multiplexer has N read inputs, a read output and a read select input, the N read inputs being coupled to the output of the plurality of N read pointer registers, the read output coupled to the read address input in the memory, and the read select input coupling one of the N read inputs to the read output.
摘要翻译：提供了不使用大量单个FIFO设备的多FIFO阵列。多FIFO阵列包括划分成多个N个部分的存储器，每个部分对应于N个FIFO之一。存储器具有写地址输入，写选通输入，数据输入，读地址输入，读选通和数据输出。还包括多个N个写入指针寄存器，具有N个写入输入的写入多路复用器，写入输出和写入选择输入，多个N个读取寄存器和读取多路复用器。每个写指针寄存器对应于N个FIFO之一，并且每个写指针寄存器保持对应于N个FIFO之一的写地址。写入多路复用器的N个写入输入耦合到多个N个写入指针寄存器的输出，写入输出耦合到存储器中输入的写入地址，并且写入选择输入将N个写入输入之一耦合到写入输出。每个读指针寄存器对应于N个FIFO之一，每个读指针寄存器保持对应于N个FIFO之一的读地址。读取多路复用器具有N个读取输入，读取输出和读取选择输入，N个读取输入耦合到多个N个读取指针寄存器的输出，耦合到在存储器中输入的读取地址的读取输出，以及读取选择输入将N个读取输入之一耦合到读取输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式