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1. 发明授权

US08014215B2 Cache array power savings through a design structure for valid bit detection 失效
标题翻译：通过用于有效位检测的设计结构来缓存阵列功耗
公开(公告)号：US08014215B2
公开(公告)日：2011-09-06
申请号：US12635234
申请日：2009-12-10
申请人： Michael J. Lee , Bao G. Truong , Samuel I. Ward
发明人： Michael J. Lee , Bao G. Truong , Samuel I. Ward
IPC分类号： G11C7/00
CPC分类号： G06F12/0895 , G06F2212/1028 , G11C11/412 , Y02D10/13
摘要： A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.
摘要翻译：提供了一种机制，用于选通已被无效的高速缓存访问存储器中的任何行的读取访问。高速缓存存取存储器中的地址解码器发送存储器访问到非门控字线驱动器和与存储器访问相关联的选通字线驱动器。响应于非门控字线驱动器将存储器访问确定为读取访问，非门控字线驱动器将存储在有效位存储器单元中的数据输出到门控字线驱动器。门控字线驱动器确定来自非门控字线驱动器的来自有效位存储器单元的数据是否响应于门控字线驱动器确定存储器访问作为读取访问而指示有效数据或无效数据，并且拒绝数据的输出在与该门控字幕驱动器相关联的一行存储器单元响应于该数据无效。

2. 发明授权

US07673204B2 Method using non-linear compression to generate a set of test vectors for use in scan testing an integrated circuit 有权
标题翻译：使用非线性压缩的方法来生成用于扫描测试集成电路的一组测试向量
公开(公告)号：US07673204B2
公开(公告)日：2010-03-02
申请号：US11773578
申请日：2007-07-05
申请人： Gahn W. Krishnakalin , Emiliano Lozano , Bao G. Truong , Samuel I. Ward
发明人： Gahn W. Krishnakalin , Emiliano Lozano , Bao G. Truong , Samuel I. Ward
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector wherein at least two of the coding schemes selected for encoding are different from one another, and wherein one of the available coding schemes represents non-encoded data. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector. Each data block is routed to a plurality of decoders, wherein each decoder is adapted to recognize only one of the coding schemes represented by one of the bit patterns. The decoder recognizing the coding scheme of the data block decodes the bit pattern of the data block and generates the test vectors corresponding to the data block.
摘要翻译：提供了一种使用非线性数据压缩的方法，以便产生用于在集成电路的扫描测试中使用的一组测试向量。该方法包括以下步骤：首先设计该组测试向量，并为每个测试向量选择多个可用编码方案中的一个，其中选择用于编码的编码方案中的至少两个彼此不同，并且其中一个可用编码方案表示非编码数据。该方法还包括操作随机模式发生器以产生数据块，每个对应于一个测试向量，其中与给定测试向量相对应的数据块用表示给定测试向量的编码方案的比特模式进行编码。相应的数据块还具有小于给定测试向量的位长度的位长度。每个数据块被路由到多个解码器，其中每个解码器适于仅识别由一个位模式表示的编码方案之一。识别数据块的编码方式的解码器对数据块的位模式进行解码，生成与数据块对应的测试矢量。

3. 发明申请

US20090094307A1 ACCURACY IMPROVEMENT IN CORDIC THROUGH PRECOMPUTATION OF THE ERROR BIAS 失效
标题翻译：通过对错误偏差进行预处理，可以提高准确度
公开(公告)号：US20090094307A1
公开(公告)日：2009-04-09
申请号：US11869022
申请日：2007-10-09
申请人： David N. Ault , Emiliano Lozano , Bao G. Truong , Samuel I. Ward
发明人： David N. Ault , Emiliano Lozano , Bao G. Truong , Samuel I. Ward
IPC分类号： G06F7/548
CPC分类号： G06F7/5446
摘要： Performing a calculation using a coordinate rotation digital computer (CORDIC) algorithm. Execution of the CORDIC algorithm is begun. An error introduced by a truncated vector as a result of executing the CORDIC algorithm is pre-computed. The error is incorporated into a subsequent iteration of the CORDIC algorithm. Execution of the CORDIC algorithm is completed. The result of the CORDIC algorithm is stored.
摘要翻译：使用坐标旋转数字计算机（CORDIC）算法进行计算。开始执行CORDIC算法。作为执行CORDIC算法的结果的截断向量引入的误差是预先计算的。该错误被并入CORDIC算法的后续迭代中。完成CORDIC算法的执行。存储CORDIC算法的结果。

4. 发明授权

US07468929B2 Apparatus for SRAM array power reduction through majority evaluation 失效
标题翻译：用于SRAM阵列功率降低的装置通过多数评估
公开(公告)号：US07468929B2
公开(公告)日：2008-12-23
申请号：US11609382
申请日：2006-12-12
申请人： Michael J. Lee , Bao G. Truong
发明人： Michael J. Lee , Bao G. Truong
IPC分类号： G11C5/14
CPC分类号： G11C7/22 , G11C11/413 , G11C2207/2227
摘要： A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed is provided. Logic is provided that identifies a polarity of a row of memory cells whose data values are to be read. The polarity of the row of memory cells indicates whether a majority of the data values stored in the row of memory cells are logic 1 data values or logic 0 data values. Based on the polarity, selection logic either selects true data values or complement data values of the memory cells. Additional logic is provided in each memory cell for outputting a true data value to a read bit line and outputting a compliment data value to the read bit line based on the polarity.
摘要翻译：提供了当SRAM阵列被访问时减少SRAM阵列消耗的功率或能量的机构。提供逻辑，其标识要读取其数据值的一行存储器单元的极性。存储单元行的极性指示存储在存储单元行中的大部分数据值是逻辑1数据值还是逻辑0数据值。基于极性，选择逻辑选择真实数据值或存储单元的补码数据值。在每个存储器单元中提供附加的逻辑，用于将真实数据值输出到读位线，并且基于极性将补码数据值输出到读位线。

5. 发明申请

US20080137450A1 APPARATUS AND METHOD FOR SRAM ARRAY POWER REDUCTION THROUGH MAJORITY EVALUATION 失效
标题翻译：通过重大评估进行SRAM阵列功率降低的装置和方法
公开(公告)号：US20080137450A1
公开(公告)日：2008-06-12
申请号：US11609382
申请日：2006-12-12
申请人： Michael J. Lee , Bao G. Truong
发明人： Michael J. Lee , Bao G. Truong
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C11/413 , G11C2207/2227
摘要： A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed are provided. Logic is provided for determining the polarity of an incoming row being written to the SRAM cell array. Logic is further provided for storing a polarity value into an additional SRAM cell per row of the SRAM cell array. Logic is also provided for reading an inverted value of the SRAM cells of a row in the SRAM cell array if the row contains more 0's than 1's, as determined based on the polarity value stored in the additional SRAM cell per row. Logic is further provided for signaling to downstream logic whether the data read from the SRAM cells in the row represents the true data values or their complement, as determined based on the polarity value stored in the additional SRAM cell per row.
摘要翻译：提供了当SRAM阵列被访问时减少SRAM阵列消耗的功率或能量的机构。逻辑被提供用于确定被写入SRAM单元阵列的输入行的极性。进一步提供逻辑用于将极性值存储到每个SRAM单元阵列的附加SRAM单元中。如果根据存储在每行的附加SRAM单元中的极性值确定的行，如果该行包含多于0的逻辑，则还提供用于读取SRAM单元阵列中的行的SRAM单元的反相值的逻辑。进一步提供逻辑用于向下游逻辑发信号，从行中的SRAM单元读取的数据是否基于存储在每行的附加SRAM单元中的极性值确定的真实数据值或其补码。

6. 发明申请

US20070283172A1 Mitigate Power Supply Noise Response by Throttling Execution Units Based Upon Voltage Sensing 失效
标题翻译：通过基于电压检测的截止执行单元来缓解电源噪声响应
公开(公告)号：US20070283172A1
公开(公告)日：2007-12-06
申请号：US11420820
申请日：2006-05-30
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.
摘要翻译：提供了一种通过基于电路中的电压感测的节流执行单元来减轻电源和配电系统噪声响应的系统。感测单元感测电路的电压。感测单元确定另一个执行单元的执行是否会导致电路电压降至阈值以下。响应于确定另一执行单元的执行将导致电路电压降低到阈值水平以下，执行单元被调节。

7. 发明授权

US07208972B2 Circuit for generating a tracking reference voltage 失效
标题翻译：用于产生跟踪参考电压的电路
公开(公告)号：US07208972B2
公开(公告)日：2007-04-24
申请号：US10845568
申请日：2004-05-13
申请人： Daniel M. Dreps , Anand Haridass , Bao G. Truong
发明人： Daniel M. Dreps , Anand Haridass , Bao G. Truong
IPC分类号： H03K17/16
CPC分类号： H04L25/061 , H04L25/45
摘要： Two or more integrated circuit (IC) chips are separated by a significant distance relative to their communication frequency such that pseudo-differential signaling is used to improve signal detection. A derived reference voltage is generated that tracks the variations of the driver and receiver side power supply variations that normally reduce noise margins. The derived reference voltage is filtered to reduce high frequency response and coupled as the reference to differential receivers used to detect the logic levels of the communication signals.
摘要翻译：两个或多个集成电路（IC）芯片相对于它们的通信频率被隔开相当长的距离，使得伪差分信号用于改善信号检测。产生导出的参考电压，其跟踪通常降低噪声容限的驱动器和接收机侧电源变化的变化。导出的参考电压被滤波以降低高频响应并作为用于检测通信信号的逻辑电平的差分接收器的参考而耦合。

8. 发明授权

US08375172B2 Preventing fast read before write in static random access memory arrays 失效
标题翻译：在写入静态随机存取存储器阵列之前防止快速读取
公开(公告)号：US08375172B2
公开(公告)日：2013-02-12
申请号：US12761618
申请日：2010-04-16
申请人： Eddie K. Chan , Michael J. Lee , Ricardo H. Nigaglioni , Bao G. Truong
发明人： Eddie K. Chan , Michael J. Lee , Ricardo H. Nigaglioni , Bao G. Truong
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C11/00 , G11C7/00
CPC分类号： G11C7/22 , G06F12/0855 , G06F12/0895 , G11C11/412 , G11C11/413
摘要： A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines whether a data input signal is in a first state or a second state. Responsive to the data input signal being in the second state, the first circuitry outputs a global write line signal in the first state. Responsive to the global write line signal being in the first state, second circuitry outputs a column select signal in the second state. Responsive to the column select signal being in the second state, third circuitry keeps a downstream read path of the cache access memory at the first state such that data output by the cache memory array is in the first state.
摘要翻译：提供了一种机制，用于在直写操作期间实现适当的写入。响应于将存储器访问确定为直写操作，第一电路确定数据输入信号是处于第一状态还是第二状态。响应于处于第二状态的数据输入信号，第一电路在第一状态下输出全局写入线信号。响应于全局写入线信号处于第一状态，第二电路输出处于第二状态的列选择信号。响应于列选择信号处于第二状态，第三电路将高速缓存存取存储器的下游读取路径保持在第一状态，使得由高速缓冲存储器阵列输出的数据处于第一状态。

9. 发明授权

US08006152B2 Scan chain fail diagnostics 有权
标题翻译：扫描链失败诊断
公开(公告)号：US08006152B2
公开(公告)日：2011-08-23
申请号：US12351950
申请日：2009-01-12
申请人： Samuel I. Ward , Patrick R. Crosby , William D. Ramsour , Bao G. Truong
发明人： Samuel I. Ward , Patrick R. Crosby , William D. Ramsour , Bao G. Truong
IPC分类号： G01R31/28
CPC分类号： G01R31/318566 , G01R31/318547
摘要： A method comprises generating a test pattern for a device under test (DUT), wherein the DUT comprises a plurality of scan chains coupled to a plurality of multiple input shift registers (MISRs). The plurality of faults detected by a first MISR and by a second MISR are identified. In the event the plurality of faults detected by the first MISR does not include any of the plurality of faults detected by the second MISR and the plurality of faults detected by the second MISR does not include any of the plurality of faults detected by the first MISR, the first MISR and the second MISR are coupled as an independent MISR pair. The test pattern is applied to the DUT to generate a scan chain output. The independent MISR pair captures the scan chain output to generate a test signature. The test signature is compared with a known good signature.
摘要翻译：一种方法包括产生被测器件（DUT）的测试图案，其中DUT包括耦合到多个多输入移位寄存器（MISR）的多个扫描链。识别由第一MISR和第二MISR检测到的多个故障。在由第一MISR检测到的多个故障不包括由第二MISR检测到的多个故障中的任何一个故障的情况下，由第二MISR检测到的多个故障不包括由第一MISR检测到的多个故障中的任何一个，第一MISR和第二MISR作为独立MISR对耦合。将测试模式应用于DUT以生成扫描链输出。独立的MISR对捕获扫描链输出以生成测试签名。将测试签名与已知的良好签名进行比较。

10. 发明授权

US07904849B2 Ceramic package in which far end noise is reduced using capacitive cancellation by offset wiring 有权
标题翻译：陶瓷封装，其中通过偏移布线使用电容消除来减少远端噪声
公开(公告)号：US07904849B2
公开(公告)日：2011-03-08
申请号：US11951705
申请日：2007-12-06
申请人： Anand Haridass , Andreas Huber , Bao G. Truong , Roger D. Weekly
发明人： Anand Haridass , Andreas Huber , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/49155 , Y10T29/49163 , H01L2924/00
摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.
摘要翻译：提供了一种用于减少由于来自多层陶瓷封装的其它信号面中的信号线的感应影响而在信号线中遭受的垂直串扰干扰的机制。利用该装置和方法，多层陶瓷封装中的一个或多个通孔可以从结构中移除以提供信号线的偏移通过的区域。由于信号线的这些偏移存在于彼此之上或之下的并行平面中，在这些信号线偏移之间没有直接存在接地线，所以在信号线中引入电容性串扰。该电容串扰与信号线已经经历的电感串扰的极性相反。结果，电容串扰倾向于消除或减少电感串扰，从而减少信号线中的远端噪声。

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