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1. 发明授权

US09354844B2 Method and apparatus for iteratively calculating a value 有权
标题翻译：用于迭代计算值的方法和装置
公开(公告)号：US09354844B2
公开(公告)日：2016-05-31
申请号：US13709450
申请日：2012-12-10
申请人： Intel Mobile Communications GmbH
发明人： Andreas Boehme , Andreas Menkhoff
IPC分类号： G06F7/544 , G06F7/548
CPC分类号： G06F7/548 , G06F7/5446
摘要： A method and an apparatus are described which determine at least one output value based on at least one input value. The input value is provided to a processing unit, wherein a combination of intermediate values is iteratively calculated. Each intermediate value is calculated during an iteration such that the intermediate value for each iteration is buffered, using a buffer storage. Based on the combination of the buffered intermediate values a storage is accessed, the storage storing a plurality of first output values, each first output value associated with a respective combination of the buffered intermediate values, so that the first output value is output.
摘要翻译：描述了基于至少一个输入值来确定至少一个输出值的方法和装置。将输入值提供给处理单元，其中迭代地计算中间值的组合。在迭代期间计算每个中间值，以便使用缓冲存储器缓冲每个迭代的中间值。基于缓冲的中间值的组合，访问存储器，存储器存储多个第一输出值，每个第一输出值与缓冲的中间值的相应组合相关联，使得输出第一输出值。

2. 发明授权

US08572152B2 CORDIC computation circuit and method 有权
标题翻译： CORDIC计算电路及方法
公开(公告)号：US08572152B2
公开(公告)日：2013-10-29
申请号：US12919632
申请日：2009-03-05
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： G06F7/38
CPC分类号： G06F7/5446 , G06T3/604
摘要： Disclosed is a CORDIC circuit in which scale correction process is divided into two stages: rough correction and fine correction, and a second-process of a pseudo-rotation process is performed in parallel with the fine scale correction. A range of the fine scale correction is set so that it is not necessary to perform a scale correction with regard to a remaining rotation angle of the first half of the pseudo-rotation process.
摘要翻译：公开了一种CORDIC电路，其中缩放校正处理被分为两个阶段：粗略校正和精细校正，并且与精细刻度校正并行执行伪旋转处理的第二处理。精确刻度校正的范围被设定为不需要对伪旋转处理的前半部分的剩余旋转角进行刻度校正。

3. 发明授权

US08572150B1 Parameterization of a CORDIC algorithm for providing a CORDIC engine 有权
标题翻译：用于提供CORDIC引擎的CORDIC算法的参数化
公开(公告)号：US08572150B1
公开(公告)日：2013-10-29
申请号：US11973093
申请日：2007-10-05
申请人： Christopher H. Dick
发明人： Christopher H. Dick
IPC分类号： G06F7/38
CPC分类号： G06F7/5446
摘要： Parameterization of a CORDIC algorithm for providing a CORDIC engine is described. An aspect of the invention is a method in a digital processing system for generation of the CORDIC engine. Numbers of fractional output bits for a user-defined numerical result format are obtained. The numbers of fractional output bits are for each of a plurality of output variables associated with the CORDIC algorithm. Micro-rotations associated with each of the plurality of output variables are determined responsive to the numbers of fractional output bits. Quantizations associated with each of the plurality of output variables are determined responsive at least in part to the numbers of fractional output bits.
摘要翻译：描述了用于提供CORDIC引擎的CORDIC算法的参数化。本发明的一个方面是用于生成CORDIC发动机的数字处理系统中的方法。获得用户定义的数字结果格式的分数输出位数。对于与CORDIC算法相关联的多个输出变量中的每一个，分数输出位的数目。响应于分数输出比特的数量确定与多个输出变量中的每一个相关联的微旋转。至少部分地响应于分数输出比特的数量来确定与多个输出变量中的每一个相关联的量化。

4. 发明申请

US20110225222A1 METHODS AND APPARATUSES FOR CORDIC PROCESSING 有权
标题翻译： CORDIC加工的方法和装置
公开(公告)号：US20110225222A1
公开(公告)日：2011-09-15
申请号：US12724302
申请日：2010-03-15
申请人： Manoj Gunwani , Harekrishna Verma
发明人： Manoj Gunwani , Harekrishna Verma
IPC分类号： G06F17/16 , G06F5/01
CPC分类号： G06F7/5446
摘要： A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array.
摘要翻译： CORDIC引擎包括N级CORDIC处理器，用于执行CORDIC算法的N个微迭代，并响应于3向量CORDIC输入生成3向量CORDIC输出。一个计数器计数CORDIC算法的M个宏迭代次数，并指示周期迭代的开始。复用器在循环迭代开始时将N级CORDIC处理器的输入选择为3向量CORDIC输入，或者在其他时间选择3向量CORDIC输出。 CORDIC算法在N * M个时钟周期之后通过为M个宏迭代中的每一个生成N个微迭代来完成。在一些实施例中，作为可编程逻辑阵列的一部分，CORDIC引擎耦合到可编程逻辑块。

5. 发明申请

US20110119520A1 Hardware Function Generator Support in a DSP 审中-公开
标题翻译： DSP中的硬件函数发生器支持
公开(公告)号：US20110119520A1
公开(公告)日：2011-05-19
申请号：US12944629
申请日：2010-11-11
申请人： Shoab A. Khan , Rehan Hameed , Hassan Farooq
发明人： Shoab A. Khan , Rehan Hameed , Hassan Farooq
IPC分类号： G06F1/06 , G06F1/02 , G06F17/15 , G06F7/548
CPC分类号： G06F7/57 , G06F7/5446 , G06F9/3867 , G06F9/3879 , G06F2207/3884
摘要： The present invention relates to digital signal processors with an integrated module configured to compute a Coordinate Rotation Digital Computer (CORDIC) in a pipeline. The pipelined module can advantageously complete computation of one CORDIC computation for each clock pulse applied to the CORDIC module, thereby providing a CORDIC computation for each clock pulse. One embodiment advantageously computes a first portion of a computation with a lookup table and a second portion in accordance with a CORDIC algorithm. Advantageously, data in a CORDIC pipeline is automatically advanced in response to read instructions and can be automatically advanced from the beginning of the pipeline to the end of the pipeline to reinitialize the pipeline. This allows information to be retrieved from the CORDIC pipeline with relatively little overhead. The automatic starting and stopping of the CORDIC pipeline advantageously allows the retrieval of computations from efficient pipeline architectures on an as-needed basis.
摘要翻译：本发明涉及具有集成模块的数字信号处理器，其被配置为在流水线中计算坐标旋转数字计算机（CORDIC）。流水线模块可以有利地完成对施加到CORDIC模块的每个时钟脉冲的一个CORDIC计算的计算，从而为每个时钟脉冲提供CORDIC计算。一个实施例有利地根据CORDIC算法利用查找表和第二部分来计算计算的第一部分。有利地，CORDIC流水线中的数据响应于读取指令而自动进行，并且可以从流水线的开始自动地前进到流水线的末端以重新初始化流水线。这允许以较少的开销从CORDIC管道检索信息。 CORDIC管道的自动启动和停止有利地允许根据需要从有效管道架构中检索计算。

6. 发明申请

US20070198625A1 Conditional negating booth multiplier 审中-公开
标题翻译：有条件否定展位乘数
公开(公告)号：US20070198625A1
公开(公告)日：2007-08-23
申请号：US11783393
申请日：2007-04-09
申请人： Arthur Torosyan
发明人： Arthur Torosyan
IPC分类号： G06F7/38
CPC分类号： G06F7/5446
摘要： An angle rotator performs angle rotation of an input complex signal in the complex plane according to an angle θ. The angle rotator includes a coarse stage rotation and a fine stage rotation. The two specific amounts of rotation are obtained directly from the original angle, without performing iterations as are performed by known CORDIC-type methods. The coarse stage rotation is performed using truncated approximations for the cosine θM and the sine θM, where θM is a radian angle that corresponds to a most significant word (MSW) of the input angle θ. The fine stage rotation is performed using one or more error values that compensate for approximations and quantization errors associated with the coarse stage rotation. By partitioning the rotation into coarse and fine rotation stages, a two stage structure is obtained that requires much less hardware than a single-stage rotator, without sacrificing angle precision. This can occur because the two-stage rotator stores pre-computed cosine θM and the sine θM values in a small lookup table (e.g. memory device) for fast retrieval. Furthermore, the angle rotator consolidates all operations into a small number of reduced-size multipliers, enabling the use of efficient multiplier implementations, such as Booth encoding, thereby yielding a smaller and faster overall circuit. When higher precision is desired, more accurate results can be attained simply by increasing the wordlength and the multiplier size, without significantly increasing overall circuit latency.
摘要翻译：角度旋转器根据角度θ执行复平面中的输入复信号的角度旋转。角度旋转器包括粗级旋转和精细级旋转。直接从原始角度获得两个特定的旋转量，而不会像已知的CORDIC型方法那样进行迭代。使用用于余弦θM和正弦θM的截距近似来执行粗阶段旋转，其中θ是与对应的弧度角到输入角θ的最高有效字（MSW）。使用补偿与粗级旋转相关联的近似和量化误差的一个或多个误差值来执行精细级旋转。通过将旋转分割成粗略和精细的旋转阶段，获得了比单级旋转器少得多的硬件的两级结构，而不牺牲角度精度。这可以发生，因为两级旋转器在小查找表（例如存储器件）中存储预计算的余弦θ和正弦值，以便快速检索。此外，角度旋转器将所有操作整合为少量的小尺寸乘法器，使得能够使用诸如布斯编码的有效乘法器实现，从而产生越来越小的总体电路。当需要更高的精度时，可以通过增加字长和乘数大小来获得更精确的结果，而不会显着增加总体电路的延迟。

7. 发明申请

US20060200510A1 Precision cordic processor 审中-公开
标题翻译：精密线性处理器
公开(公告)号：US20060200510A1
公开(公告)日：2006-09-07
申请号：US11346754
申请日：2006-01-30
申请人： Cindy Wang , Xiangyang Xu , Xiaochun Chen
发明人： Cindy Wang , Xiangyang Xu , Xiaochun Chen
IPC分类号： G06F15/00
CPC分类号： G06F7/4818 , G06F7/49921 , G06F7/49947 , G06F7/5446 , H04L27/227 , H04L2027/0026 , H04L2027/003
摘要： A CORDIC angle calculator for a baseband IC receiver incorporates a CORDIC algorithm calculating processor with an input scaling means receiving input data, scaling the input data and providing it to the CORDIC processor. An output scaling means receives output data from the CORDIC processor and rescales the output data to provide a calculated angle. In an exemplary embodiment, the input scaling means includes means for shifting the input data for bit reduction and providing a shift signal corresponding to the input data shift and wherein the output scaling means is responsive to the shift signal.
摘要翻译：用于基带IC接收机的CORDIC角度计算器包括CORDIC算法计算处理器和输入缩放装置接收输入数据，缩放输入数据并将其提供给CORDIC处理器。输出缩放装置从CORDIC处理器接收输出数据并重新调整输出数据以提供计算出的角度。在示例性实施例中，输入缩放装置包括用于移位用于比特减少的输入数据并提供对应于输入数据移位的移位信号的装置，并且其中输出缩放装置响应于移位信号。

8. 发明申请

US20050015418A1 Real-time implementation of field programmable gate arrays (FPGA) design in hyperspectral imaging 失效
标题翻译：在高光谱成像中实时实现现场可编程门阵列（FPGA）设计
公开(公告)号：US20050015418A1
公开(公告)日：2005-01-20
申请号：US10875102
申请日：2004-06-24
申请人： Chein-I Chang , Jianwei Wang
发明人： Chein-I Chang , Jianwei Wang
IPC分类号： G06F7/38 , G06F7/544 , G06F17/11 , G06T5/00 , G06T5/20
CPC分类号： G06K9/00986 , G06F7/5446 , G06F17/11 , G06K9/0063 , G06T7/11 , G06T7/194 , G06T2200/28 , G06T2207/10036 , G06T2207/30212
摘要： A Field Programmable Gate Arrays (FPGA) design uses a Coordinate Rotation DIgital Computer (CORDIC) algorithm that can convert a Givens rotation of a vector to a set of shift-add operations. The CORDIC algorithm can be easily implemented in hardware architecture, therefore in FPGA. Since the computation of the inverse of the data correlation matrix involves a series of Givens rotations, the utility of the CORDIC algorithm allows a causal Constrained Energy Minimization (CEM) to perform real-time processing in FPGA. An FPGA implementation of the causal CEM is described and its detailed architecture is also described.
摘要翻译：现场可编程门阵列（FPGA）设计使用坐标旋转二进制计算机（CORDIC）算法，可将矢量的Givens旋转转换为一组移位加法运算。 CORDIC算法可以在硬件体系结构中轻松实现，因此可以在FPGA中实现。由于数据相关矩阵的逆的计算涉及一系列Givens旋转，因此CORDIC算法的实用性允许因果约束能量最小化（CEM）在FPGA中执行实时处理。描述了因果CEM的FPGA实现，并对其详细架构进行了描述。

9. 发明授权

US06349317B1 Efficient radix-4 CORDIC vector rotators and computers of sine and cosine functions 失效
标题翻译：高效的radix-4 CORDIC向量旋转器和正弦和余弦函数的计算机
公开(公告)号：US06349317B1
公开(公告)日：2002-02-19
申请号：US09267762
申请日：1999-03-13
申请人： Vitit Kantabutra
发明人： Vitit Kantabutra
IPC分类号： G06F1716
CPC分类号： G06F7/5446
摘要： An improved radix-4 CORDIC rotator iteration stage, using answer digits {−3, −1, 1, 3} instead of the conventional choices of {−3, −2, −1, 0,1, 2, 3} or {−2, −1, 0, 1, 2}, thereby achieving constant magnitude amplification. The invention includes an answer digit decision module, which normally examines only a few digits of the remainder angle &thgr;i−1, thereby saving time when compared to full-length comparison. Very rarely does the answer digit decision process involves examining close to all the digits of the remainder angle. When examining only a few digits of the remainder angle, the circuit takes only approximately 20% longer than a radix-2 CORDIC stage. The invented rotator stage is usable either as a pipeline stage or as a single-stage iterative circuit. For use in a pipeline, the invented stage is to be used only when only a few remainder angle bits need to be examined.
摘要翻译：改进的radix-4 CORDIC旋转迭代阶段，使用答案数字{-3，-1,1,3}，而不是常规的{-3，-2，-1，0,1,2,3}或{ -2，-1,0,1,2}，从而实现恒定幅度放大。本发明包括一个应答数字决定模块，它通常仅检查余数角度的几位数字，从而与全长比较相比节省了时间。答案数字确定过程很少涉及检查靠近余数角度的所有数字。当仅检查剩余角度的几位数字时，该电路仅比基数-2 CORDIC级更长约20％。本发明的旋转台可用作流水线阶段或单级迭代电路。为了在管道中使用，本发明的级仅在需要检查几个剩余角度位时使用。

10. 发明授权

US6011448A Method and apparatus for frequency modulation synthesis 失效
标题翻译：用于频率调制合成的方法和装置
公开(公告)号：US6011448A
公开(公告)日：2000-01-04
申请号：US949574
申请日：1997-10-14
申请人： Daniel H. McCabe , Peter Alexander Manson
发明人： Daniel H. McCabe , Peter Alexander Manson
IPC分类号： G06F7/544 , G10H7/00 , G10H5/00 , G06F1/02
CPC分类号： G06F7/5446 , G10H7/00 , G10H2250/475
摘要： A method for frequency modulation synthesis and apparatus for performing the method. The method uses additions rather than multiplies and therefore saves the space and cost of multipliers in circuit implementations. The method saves further resources by using the coordinate rotation digital computer (CORDIC) algorithm to acquire sine values as opposed to an extensive sine look-up table. The method can be implemented with either a dedicated digital circuit or a programmed special purpose processor such as a digital signal processor. The hardware for implementing the method is normally integrated onto a semiconductor device.
摘要翻译：一种用于频率调制合成的方法和用于执行该方法的装置。该方法使用加法而不是乘法，从而节省乘法器在电路实现中的空间和成本。该方法通过使用坐标旋转数字计算机（CORDIC）算法来获得正弦值而不是广泛的正弦查找表来节省更多的资源。该方法可以使用专用数字电路或诸如数字信号处理器的编程专用处理器来实现。用于实现该方法的硬件通常集成在半导体器件上。

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