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1. 发明申请

US20070037350A1 Flash memory cell having reduced floating gate to floating gate coupling 有权
标题翻译：具有减小的浮动栅极到浮动栅极耦合的闪存单元
公开(公告)号：US20070037350A1
公开(公告)日：2007-02-15
申请号：US11582881
申请日：2006-10-17
申请人： Been-jon Woo , Yudong Kim , Albert Fazio
发明人： Been-jon Woo , Yudong Kim , Albert Fazio
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.
摘要翻译：根据本发明的实施例，闪存单元包括第一栅极堆叠和第二栅极堆叠，其具有沉积在第一和第二栅极堆叠之间的间隙的膜，使得膜在第一和第二栅极堆叠之间产生空隙。电介质材料可用于降低两个叠层之间的导电性。耐导电性的介电材料具有低介电常数（k）。最低k电介质材料是具有大约1的介电常数的空气。通过在两个栅极堆叠之间产生空隙，最少的导电材料（空气）留下填充栅极叠层之间的空间以及寄生的可能性两个相邻浮动栅极的耦合大大减小。

2. 发明授权

US5196361A Method of making source junction breakdown for devices with source-side erasing 失效
标题翻译：源端擦除器件源极结击穿的方法
公开(公告)号：US5196361A
公开(公告)日：1993-03-23
申请号：US700512
申请日：1991-05-15
申请人： Tong-Chern Ong , Been-Jon Woo
发明人： Tong-Chern Ong , Been-Jon Woo
IPC分类号： H01L21/336 , H01L27/115 , H01L29/788
CPC分类号： H01L29/66825 , H01L29/7883 , H01L29/7885 , H01L27/115
摘要： A method for making a device and the device itself which utilizes selectively doping part of the channel directly adjacent to the source to improve source-channel junction breakdown voltage is disclosed. This is accomplished through reduced dopant incorporation in the channel directly adjacent to the source during the channel doping steps. The portion of the channel which receives less channel dopant should not be so great that the charging of the floating gate is significantly altered.
摘要翻译：公开了一种制造器件和器件本身的方法，其利用选择性地掺杂与源极相邻的沟道的一部分来改善源极结击穿电压。这通过在沟道掺杂步骤期间通过与源极直接相邻的沟道中的掺杂剂掺杂减少来实现。接收较少通道掺杂剂的通道的部分不应该太大，使得浮动栅极的充电被显着改变。

3. 发明授权

US4784965A Source drain doping technique 失效
标题翻译：源极漏极掺杂技术
公开(公告)号：US4784965A
公开(公告)日：1988-11-15
申请号：US097532
申请日：1987-09-16
申请人： Been-Jon Woo , Mark A. Holler , Ender Hokeler , Sandra S. Lee
发明人： Been-Jon Woo , Mark A. Holler , Ender Hokeler , Sandra S. Lee
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66598 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7836 , Y10S148/053 , Y10S148/082 , Y10S148/106
摘要： A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.
摘要翻译：描述了形成金属氧化物半导体场效应晶体管（MOSFET）的方法，其中源极和漏极区域以基本上垂直于衬底表面的方式通过离子注入以两个步骤设置，使得杂质的浓度随着横向距离而增加远离栅极电极部件抑制热注入，防止沟道效应，增加穿通电压并增加栅极辅助击穿电压。

4. 发明授权

US4757026A Source drain doping technique 失效
标题翻译：源极漏极掺杂技术
公开(公告)号：US4757026A
公开(公告)日：1988-07-12
申请号：US97539
申请日：1987-09-16
申请人： Been-Jon Woo , Mark A. Holler , Ender Hokelek , Sandra S. Lee
发明人： Been-Jon Woo , Mark A. Holler , Ender Hokelek , Sandra S. Lee
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66598 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7836 , Y10S148/082 , Y10S148/106
摘要： A method of forming complementary metal oxide semiconductor field-effect transistors (CMOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effects, to increase punch through voltage and to increase gate-aided breakdown voltage.
摘要翻译：描述了形成互补金属氧化物半导体场效应晶体管（CMOSFET）的方法，其中源极和漏极区域以基本上垂直于衬底表面的方式通过离子注入以两个步骤设置，使得杂质的浓度随着侧向距离栅电极部件的距离，以抑制热注入，防止通道效应，增加穿通电压并增加栅极辅助击穿电压。

5. 发明授权

US07632736B2 Self-aligned contact formation utilizing sacrificial polysilicon 有权
公开(公告)号：US07632736B2
公开(公告)日：2009-12-15
申请号：US12002752
申请日：2007-12-18
申请人： Max Wei , Been-Jon Woo
发明人： Max Wei , Been-Jon Woo
IPC分类号： H01L21/76 , H01L21/265 , H01L21/425 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76897
摘要： In general, in one aspect, a method includes forming a spacer layer over a substrate having patterned stacks formed therein and trenches between the patterned stacks. A sacrificial polysilicon layer is deposited over the substrate to fill the trenches. A patterning layer is deposited over the substrate and patterned to define contact regions over at least a portion of the trenches. The sacrificial polysilicon layer is etched using the patterned patterning layer to form open regions.

6. 发明申请

US20050090100A1 Simplified dual damascene process 失效
标题翻译：简化双镶嵌工艺
公开(公告)号：US20050090100A1
公开(公告)日：2005-04-28
申请号：US10968103
申请日：2004-10-20
申请人： Been Jon Woo
发明人： Been Jon Woo
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76808
摘要： A simplified dual damascene process is disclosed. In the dual damascene process, a semiconductor substrate with MOS devices having a first metal layer, an etch stopping layer, and a dielectric layer in sequence are formed thereon. A via is formed on the dielectric layer by lithography. An organic layer is then formed. A trench is formed on the dielectric layer by the organic layer, thereby forming a dual damascene structure comprised of the trench and the via. The present invention is directed to a simplified dual damascene process, which can obtain a better trench profile without increasing the dielectric constant of the inter-metal dielectric (IMD).
摘要翻译：公开了一种简化的双镶嵌工艺。在双镶嵌工艺中，在其上形成具有第一金属层，蚀刻停止层和电介质层的具有MOS器件的半导体衬底。通过光刻在电介质层上形成通孔。然后形成有机层。通过有机层在电介质层上形成沟槽，从而形成由沟槽和通路构成的双镶嵌结构。本发明涉及一种简化的双镶嵌工艺，其可以在不增加金属间电介质（IMD）的介电常数的情况下获得更好的沟槽轮廓。

7. 发明授权

US5470772A Silicidation method for contactless EPROM related devices 失效
标题翻译：无接触EPROM相关器件的硅化方法
公开(公告)号：US5470772A
公开(公告)日：1995-11-28
申请号：US67269
申请日：1993-05-24
申请人： Been-Jon Woo
发明人： Been-Jon Woo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash contactless EPROM or EEPROM type. The array of memory cells in these devices have elongated, parallel source and drain regions disposed beneath field oxide regions. The word lines are elongated, parallel strips of polysilicon. A series of SiO.sub.2 depositions using TEOS chemistry in a PECVD process, and etches using sputter etch and plasma processes, is performed. After deposition and etchback, the polysilicon word lines remain exposed while all previous exposed substrate regions between source and drain are covered with SiO.sub.2. A metal deposition and silicidation are performed forming a silicide on the exposed silicon word lines thereby lowering the resistance of the word lines. Since the substrate regions between source and drain is covered between SiO.sub.2 prior to metal deposition and silicidation no silicide is formed in these regions. Therefore the word lines are silicidized in a self aligned process with no need for a photolithographic step after SiO.sub.2 deposition.
摘要翻译：一种用于制造闪存非接触式EPROM或EEPROM类型的非接触电可编程和电可擦除存储单元的工艺。这些器件中的存储器单元阵列具有设置在场氧化物区域之下的细长的平行的源极和漏极区域。字线是细长的，平行的多晶硅条。在PECVD工艺中使用TEOS化学的一系列SiO 2沉积和使用溅射蚀刻和等离子体处理的蚀刻进行。在沉积和回蚀之后，多晶硅字线保持暴露，而源极和漏极之间的所有先前暴露的衬底区域被SiO 2覆盖。进行金属沉积和硅化，在暴露的硅字线上形成硅化物，从而降低字线的电阻。由于源极和漏极之间的衬底区域在金属沉积和硅化之前被覆盖在SiO 2之间，所以在这些区域中不形成硅化物。因此，在自对准工艺中，字线被硅化，在SiO 2沉积之后不需要光刻步骤。

8. 发明授权

US4833099A Tungsten-silicide reoxidation process including annealing in pure nitrogen and subsequent oxidation in oxygen 失效
标题翻译：硅化钨再氧化工艺，包括在纯氮中退火，随后在氧气中氧化
公开(公告)号：US4833099A
公开(公告)日：1989-05-23
申请号：US142906
申请日：1988-01-07
申请人： Been-Jon Woo
发明人： Been-Jon Woo
IPC分类号： H01L21/321 , H01L21/336 , H01L21/8238 , H01L29/423
CPC分类号： H01L29/6659 , H01L21/32105 , H01L21/823835 , H01L29/4232 , Y10S148/003 , Y10S148/118 , Y10S148/147
摘要： A tungsten silicide reoxidation technique for forming a reoxidation layer in a CMOS device is disclosed. After forming an insulated gate member, which has a silicon-rich tungsten silicide layer overlying a polysilicon layer, it is first oxidized and the oxide is removed to expose WSi for forming a particular source/drain doped device. Then it is annealed in a substantially pure nitrogen ambient for a given time period. A subsequent growth of the reoxidation layer over the gate member by introducing oxygen results in a substantially planarized surface. The combination between tungsten and oxygen is prevented.
摘要翻译：公开了一种用于在CMOS器件中形成再氧化层的硅化钨再氧化技术。在形成具有覆盖多晶硅层的富含硅的硅化钨层的绝缘栅极部件之后，首先将其氧化并除去氧化物以暴露WSi以形成特定的源极/漏极掺杂器件。然后将其在基本上纯的氮气环境中退火给定的时间段。通过引入氧在栅极部件上的再氧化层的随后生长导致基本平坦化的表面。防止钨和氧之间的组合。

9. 发明授权

US4728617A Method of fabricating a MOSFET with graded source and drain regions 失效
标题翻译：制造具有分级源极和漏极区域的MOSFET的方法
公开(公告)号：US4728617A
公开(公告)日：1988-03-01
申请号：US926733
申请日：1986-11-04
申请人： Been-Jon Woo , Mark A. Holler , Ender Hokelek , Sandra S. Lee
发明人： Been-Jon Woo , Mark A. Holler , Ender Hokelek , Sandra S. Lee
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66598 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7836 , Y10S148/053 , Y10S148/082 , Y10S148/106 , Y10S438/965
摘要： A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.
摘要翻译：描述了形成金属氧化物半导体场效应晶体管（MOSFET）的方法，其中源极和漏极区域以基本上垂直于衬底表面的方式通过离子注入以两个步骤设置，使得杂质的浓度随着横向距离而增加远离栅极电极部件抑制热注入，防止沟道效应，增加穿通电压并增加栅极辅助击穿电压。

10. 发明申请

US20090001440A1 Semiconductor device with buried source rail 审中-公开
标题翻译：半导体器件埋地源轨
公开(公告)号：US20090001440A1
公开(公告)日：2009-01-01
申请号：US11821875
申请日：2007-06-26
申请人： Max Wei , Been-Jon Woo
发明人： Max Wei , Been-Jon Woo
IPC分类号： H01L29/788 , H01L21/70
CPC分类号： H01L27/115 , H01L27/11521
摘要： In one embodiment of the invention, a NOR Flash memory includes a buried source rail that directly connects to a source strap. Furthermore, a drain plug connects directly to a bit line.
摘要翻译：在本发明的一个实施例中，NOR闪存包括直接连接到源极带的埋入式源极轨。此外，排水塞直接连接到位线。

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