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1. 发明授权

US07973302B2 Forming phase change memory cells 有权
标题翻译：形成相变存储单元
公开(公告)号：US07973302B2
公开(公告)日：2011-07-05
申请号：US12346666
申请日：2008-12-30
申请人： Yudong Kim , Fabio Pellizzer
发明人： Yudong Kim , Fabio Pellizzer
IPC分类号： H01L29/02 , H01L47/00 , H01L29/04
CPC分类号： H01L45/06 , H01L27/2445 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1691
摘要： Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore.
摘要翻译：可以通过在衬底上形成分段加热器来形成小相变存储器单元。停止层可以形成在加热器层上并且与加热器层分段。然后，侧壁间隔物可以形成在分段加热器上方，以在侧壁间隔物之间形成孔，其可用作蚀刻分段加热器上的停止层的掩模。作为使用侧壁间隔物作为掩模的蚀刻的结果，可以在加热器上形成亚光刻孔。相变材料可以在孔内形成。

2. 发明申请

US20070111492A1 Structured, electrically-formed floating gate for flash memories 有权
标题翻译：用于闪存的结构化，电气形式的浮动栅极
公开(公告)号：US20070111492A1
公开(公告)日：2007-05-17
申请号：US11274622
申请日：2005-11-14
申请人： Charles Kuo , Yudong Kim
发明人： Charles Kuo , Yudong Kim
IPC分类号： H01L21/3205
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/6653 , H01L29/66553
摘要： Semiconductor memory devices and methods to fabricate thereof are described. A first gate base is formed on a first insulating layer on a substrate. A first gate fin is formed on the first gate base. The first gate fin has a top and sidewalls. Next, a second insulating layer is formed on the top and sidewalls of the first gate fin and portions of the first gate base. A second gate is formed on the second insulating layer. Source and drain regions are formed in the substrate at opposite sides of the first gate base. In one embodiment, the first gate fin includes an undoped polysilicon and the first gate base includes an n-type polysilicon. In another embodiment, the first gate fin includes an undoped amorphous silicon and the first gate base includes an n-type amorphous silicon.
摘要翻译：描述半导体存储器件及其制造方法。在基板上的第一绝缘层上形成第一栅极基底。第一栅极鳍形成在第一栅极基底上。第一个门鳍具有顶部和侧壁。接下来，在第一栅极鳍的顶部和侧壁以及第一栅极基底的一部分上形成第二绝缘层。第二栅极形成在第二绝缘层上。源极和漏极区域形成在第一栅极基极的相对侧的衬底中。在一个实施例中，第一栅极鳍包括未掺杂多晶硅，第一栅极基底包括n型多晶硅。在另一个实施例中，第一栅极鳍包括未掺杂的非晶硅，第一栅极基底包括n型非晶硅。

3. 发明申请

US20060073631A1 Phase change memory with damascene memory element 有权
公开(公告)号：US20060073631A1
公开(公告)日：2006-04-06
申请号：US10949090
申请日：2004-09-24
申请人： Ilya Karpov , Charles Kuo , Yudong Kim , Fabio Pellizzer
发明人： Ilya Karpov , Charles Kuo , Yudong Kim , Fabio Pellizzer
IPC分类号： H01L21/06
CPC分类号： H01L45/1683 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/16
摘要： A phase change material may be formed within a trench in a first layer to form a damascene memory element and in an overlying layer to form a threshold device. Below the first layer may be a wall heater. The wall heater that heats the overlying phase change material may be formed in a U-shape in some embodiments of the present invention. The phase change material for the memory element may be elongated in one direction to provide greater alignment tolerances with said heater and said threshold device.

4. 发明授权

US09203024B2 Copper compatible chalcogenide phase change memory with adjustable threshold voltage 有权
公开(公告)号：US09203024B2
公开(公告)日：2015-12-01
申请号：US11881080
申请日：2007-07-25
申请人： Yudong Kim , Charles C. Kuo , Gianpaolo Spadini
发明人： Yudong Kim , Charles C. Kuo , Gianpaolo Spadini
IPC分类号： H01L21/00 , H01L21/06 , H01L45/00 , H01L27/24
CPC分类号： H01L45/144 , H01L27/24 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683
摘要： A phase change memory cell may include two or more stacked or unstacked series connected memory elements. The cell has a higher, adjustable threshold voltage. A copper diffusion plug may be provided within a pore over a copper line. By positioning the plug below the subsequent chalcogenide layer, the plug may be effective to block copper diffusion upwardly into the pore and into the chalcogenide material. Such diffusion may adversely affect the electrical characteristics of the chalcogenide layer.

5. 发明授权

US08222627B2 Process for manufacturing a copper compatible chalcogenide phase change memory element and corresponding phase change memory element 有权
标题翻译：用于制造铜兼容的硫族化物相变存储元件和相应的相变存储元件的工艺
公开(公告)号：US08222627B2
公开(公告)日：2012-07-17
申请号：US12174462
申请日：2008-07-16
申请人： Charles Kuo , Yudong Kim
发明人： Charles Kuo , Yudong Kim
IPC分类号： H01L45/00 , H01L21/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/1266 , H01L45/141 , H01L45/144 , H01L45/1683
摘要： A copper-diffusion plug 21 is provided within a pore in dielectric layer over a copper signal line. By positioning the plug below a chalcogenide region, the plug is effective to block copper diffusion upwardly into the pore and into the chalcogenide region and thus to avoid adversely affecting the electrical characteristics of the chalcogenide region.
摘要翻译：铜扩散塞21设置在铜信号线上的电介质层的孔内。通过将塞子定位在硫族化物区域下方，塞子有效地阻止铜扩散到孔中并进入硫族化物区域，从而避免不利地影响硫族化物区域的电特性。

6. 发明申请

US20110223738A1 FORMING PHASE CHANGE MEMORY CELLS 有权
标题翻译：形成相变记忆细胞
公开(公告)号：US20110223738A1
公开(公告)日：2011-09-15
申请号：US13114966
申请日：2011-05-24
申请人： Yudong Kim , Fabio Pellizzer
发明人： Yudong Kim , Fabio Pellizzer
IPC分类号： H01L21/62 , B05D3/10 , C23F1/00
CPC分类号： H01L45/06 , H01L27/2445 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1691
摘要： Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore.
摘要翻译：可以通过在衬底上形成分段加热器来形成小相变存储器单元。停止层可以形成在加热器层上并且与加热器层分段。然后，侧壁间隔物可以形成在分段加热器上方，以在侧壁间隔物之间形成孔，其可用作蚀刻分段加热器上的停止层的掩模。作为使用侧壁间隔物作为掩模的蚀刻的结果，可以在加热器上形成亚光刻孔。相变材料可以在孔内形成。

7. 发明申请

US20110155986A1 DUAL RESISTANCE HEATER FOR PHASE CHANGE DEVICES AND MANUFACTURING METHOD THEREOF 有权
标题翻译：用于相变装置的双电阻加热器及其制造方法
公开(公告)号：US20110155986A1
公开(公告)日：2011-06-30
申请号：US12980141
申请日：2010-12-28
申请人： Yudong Kim , Ilya V. Karpov , Charles C. Kuo , Greg Atwood , Maria Santina Marangon , Tyler Lowrey
发明人： Yudong Kim , Ilya V. Karpov , Charles C. Kuo , Greg Atwood , Maria Santina Marangon , Tyler Lowrey
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/16 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/141 , H01L45/1683
摘要： A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface of the heater material relative to the remainder of the heater material. As a result, the portion of the heater material approximate to the phase change material region is a highly effective heater because of its high resistance, but the bulk of the heater material is not as resistive and, thus, does not increase the voltage drop and the current usage of the device.
摘要翻译：通过沉积电阻材料形成用于相变材料区域的双电阻加热器。然后将加热器材料暴露于植入或等离子体，这增加了加热器材料表面相对于加热器材料的剩余部分的电阻。结果，由于加热材料的高电阻，加热器材料的部分接近相变材料区域是高效的加热器，而是加热器材料的体积不是电阻的，因此不会增加电压降，当前使用的设备。

8. 发明授权

US07847333B2 Structured, electrically-formed floating gate for flash memories 失效
标题翻译：用于闪存的结构化，电气形式的浮动栅极
公开(公告)号：US07847333B2
公开(公告)日：2010-12-07
申请号：US12055216
申请日：2008-03-25
申请人： Charles Kuo , Yudong Kim
发明人： Charles Kuo , Yudong Kim
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/6653 , H01L29/66553
摘要： Semiconductor memory devices and methods to fabricate thereof are described. A first gate base is formed on a first insulating layer on a substrate. A first gate fin is formed on the first gate base. The first gate fin has a top and sidewalls. Next, a second insulating layer is formed on the top and sidewalls of the first gate fin and portions of the first gate base. A second gate is formed on the second insulating layer. Source and drain regions are formed in the substrate at opposite sides of the first gate base. In one embodiment, the first gate fin includes an undoped polysilicon and the first gate base includes an n-type polysilicon. In another embodiment, the first gate fin includes an undoped amorphous silicon and the first gate base includes an n-type amorphous silicon.
摘要翻译：描述半导体存储器件及其制造方法。在基板上的第一绝缘层上形成第一栅极基底。第一栅极鳍形成在第一栅极基底上。第一个门鳍具有顶部和侧壁。接下来，在第一栅极鳍的顶部和侧壁以及第一栅极基底的一部分上形成第二绝缘层。第二栅极形成在第二绝缘层上。源极和漏极区域形成在第一栅极基极的相对侧的衬底中。在一个实施例中，第一栅极鳍包括未掺杂多晶硅，第一栅极基底包括n型多晶硅。在另一个实施例中，第一栅极鳍包括未掺杂的非晶硅，第一栅极基底包括n型非晶硅。

9. 发明申请

US20070259479A1 Forming phase change memory arrays 审中-公开
公开(公告)号：US20070259479A1
公开(公告)日：2007-11-08
申请号：US11827223
申请日：2007-07-11
申请人： Charles Kuo , Ilya Karpov , Yudong Kim , Greg Atwood
发明人： Charles Kuo , Ilya Karpov , Yudong Kim , Greg Atwood
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L27/2427 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/1675 , H01L45/1691 , Y10S438/947
摘要： A phase change memory may be formed to have a dimension that is sub-lithographic in one embodiment by forming a surface feature over the phase change material, and coating the surface feature with a mask of sub-lithographic dimensions. The horizontal portions of the mask and the surface feature may then be removed and the remaining portions of the mask may be used to define a dimension of said phase change material. Another dimension of the phase change material may be defined using an upper electrode extending over said phase change material as a mask to etch the phase change material.

10. 发明授权

US06265292B1 Method of fabrication of a novel flash integrated circuit 有权
标题翻译：一种新颖的闪存集成电路的制造方法
公开(公告)号：US06265292B1
公开(公告)日：2001-07-24
申请号：US09351498
申请日：1999-07-12
申请人： Krishna Parat , Raghupathy V. Giridhar , Cheng C. Hu , Daniel Xu , Yudong Kim , Glen Wada
发明人： Krishna Parat , Raghupathy V. Giridhar , Cheng C. Hu , Daniel Xu , Yudong Kim , Glen Wada
IPC分类号： H01L21425
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： A method of fabricating a flash memory integrated circuit is described. In an embodiment of the present invention a dielectric filled trench isolation region is formed in a silicon substrate. The dielectric filled trench isolation region isolates a first portion of the silicon substrate from a second portion of the silicon substrate. A portion of the dielectric in the trench is then removed to reveal a portion of the silicon substrate in the trench between the first and second portions of the silicon substrate. Ions are then implanted to form a first source region in the first portion of the silicon substrate and to form a second source region in the second portion of the silicon substrate and to form a doped region in the revealed silicon substrate in the trench wherein the doped region in the trench extends from the first doped source region to the second doped source region.
摘要翻译：描述了制造闪速存储器集成电路的方法。在本发明的一个实施例中，在硅衬底中形成介质填充沟槽隔离区。电介质填充沟槽隔离区域将硅衬底的第一部分与硅衬底的第二部分隔离。然后去除沟槽中的电介质的一部分，以在硅衬底的第一和第二部分之间的沟槽中露出硅衬底的一部分。然后植入离子以在硅衬底的第一部分中形成第一源极区域，并在硅衬底的第二部分中形成第二源极区域，并且在沟槽中的透明硅衬底中形成掺杂区域，其中掺杂沟槽中的区域从第一掺杂源区延伸到第二掺杂源区。

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