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1. 发明授权

US09325534B2 Configurable differential to single ended IO 有权
标题翻译：可配置差分至单端IO
公开(公告)号：US09325534B2
公开(公告)日：2016-04-26
申请号：US12568765
申请日：2009-09-29
申请人： Frank D. Ferraiolo , Kevin C. Gower , Robert B. Tremaine , Kenneth L. Wright
发明人： Frank D. Ferraiolo , Kevin C. Gower , Robert B. Tremaine , Kenneth L. Wright
IPC分类号： H04B3/00 , H04L25/02
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译：一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。传输幅度和数据的单端或差分传输是功率模式的例子。控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。

2. 发明授权

US08869007B2 Three dimensional (3D) memory device sparing 有权
标题翻译：三维（3D）存储设备备用
公开(公告)号：US08869007B2
公开(公告)日：2014-10-21
申请号：US13523091
申请日：2012-06-14
申请人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
发明人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
IPC分类号： G11C29/00 , G06F11/10 , G11C29/44 , H03M13/05
CPC分类号： G06F11/1072 , G06F11/1048 , G11C5/04 , G11C11/40 , G11C29/4401 , G11C29/886 , G11C2029/0409 , H03M13/05
摘要： According to one embodiment of the present invention, a method for operating a three dimensional (“3D”) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code.
摘要翻译：根据本发明的一个实施例，一种用于操作三维（“3D”）存储器件的方法包括由存储器控制器检测3D存储器件上的第一个错误，并由存储器控制器检测第二个错误在3D存储器件的第一级中的第一芯片中，其中第一芯片具有相关的第一芯片选择。该方法还包括对第二级别的第二芯片供电，从存储器控制器向3D存储器件发送命令以将第一芯片中的第一芯片替换为第二芯片，并使用错误控制代码校正第一错误。

3. 发明授权

US08862944B2 Isolation of faulty links in a transmission medium 有权
标题翻译：隔离传输介质中的故障链路
公开(公告)号：US08862944B2
公开(公告)日：2014-10-14
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright , Lisa C. Gower
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/00 , G06F11/20 , G06F11/10 , H04L1/00
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links. An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译：隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法。检测到错误状况，并且确定错误状况被隔离到单个传输链路。在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。

4. 发明申请

US20130151790A1 Efficient Storage of Meta-Bits Within a System Memory 失效
公开(公告)号：US20130151790A1
公开(公告)日：2013-06-13
申请号：US13611909
申请日：2012-09-12
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G06F12/08
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

5. 发明申请

US20110320881A1 ISOLATION OF FAULTY LINKS IN A TRANSMISSION MEDIUM 有权
标题翻译：在传输介质中分离故障链路
公开(公告)号：US20110320881A1
公开(公告)日：2011-12-29
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/34
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译：隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法检测到错误状况，并且确定错误状况被隔离为单个传输链路。在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。

6. 发明申请

US20100293438A1 System to Improve Error Correction Using Variable Latency and Associated Methods 有权
标题翻译：使用变量延迟和相关方法改进误差校正的系统
公开(公告)号：US20100293438A1
公开(公告)日：2010-11-18
申请号：US12023546
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048
摘要： A system to improve error correction may include a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system may also include a slow decoder to possibly correct the uncorrectable error in a data packet based upon the at least two data packets.
摘要翻译：用于改进纠错的系统可以包括处理数据分组的快速解码器，直到快速解码器在数据分组中发现对于至少两个数据分组的请求产生的不可校正的错误。该系统还可以包括慢解码器，以可能地基于至少两个数据分组校正数据分组中的不可校正错误。

7. 发明授权

US07487397B2 Method for cache correction using functional tests translated to fuse repair 失效
标题翻译：使用功能测试翻译保险丝修复的缓存校正方法
公开(公告)号：US07487397B2
公开(公告)日：2009-02-03
申请号：US11260562
申请日：2005-10-27
申请人： Walter R. Lockwood , Ryan J. Pennington , Hugh Shen , Kenneth L. Wright
发明人： Walter R. Lockwood , Ryan J. Pennington , Hugh Shen , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.
摘要翻译：一种通过操作微处理器来执行利用高速缓冲存储器的功能测试程序来校正诸如高速缓存存储器的微处理器的存储阵列中的缺陷的方法，在功能测试程序期间收集跟踪阵列中的故障数据，使用故障数据在高速缓冲存储器中定位缺陷，以及通过设置保险丝将该位置的访问请求重新路由到冗余阵列来修复缺陷。故障数据可能包括错误综合征和故障地址。功能测试过程创建随机高速缓存访问序列，其使用基于随机种子的测试模式在高速缓冲存储器中引起变化的流量负载。功能测试程序可以在完成设置一些保险丝的微处理器的非功能性内置自检之后完成。

8. 发明授权

US09519480B2 Branch target preloading using a multiplexer and hash circuit to reduce incorrect branch predictions 有权
标题翻译：分支目标预加载使用多路复用器和散列电路来减少不正确的分支预测
公开(公告)号：US09519480B2
公开(公告)日：2016-12-13
申请号：US12029258
申请日：2008-02-11
申请人： Gregory W. Alexander , Anton Blanchard , Milton D. Miller, II , Todd A. Venton , Kenneth L. Wright
发明人： Gregory W. Alexander , Anton Blanchard , Milton D. Miller, II , Todd A. Venton , Kenneth L. Wright
IPC分类号： G06F9/312 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3005 , G06F9/3804 , G06F9/3806
摘要： A system provides complex branch execution hardware and a hardware-based Multiplexer (MUX) to multiplex a fetch address of a future branch and a preloaded branch fetch address to create an index hash value that is used to index a branch target prediction table for execution by a processor core, in order to reduce branch mis-prediction by preloading.
摘要翻译：系统提供复杂的分支执行硬件和基于硬件的多路复用器（MUX）来复用未来分支的提取地址和预加载的分支提取地址，以创建用于索引分支目标预测表以执行的索引散列值处理器核心，以便通过预加载减少分支误预测。

9. 发明授权

US08775904B2 Efficient storage of meta-bits within a system memory 有权
标题翻译：元位在系统存储器内的高效存储
公开(公告)号：US08775904B2
公开(公告)日：2014-07-08
申请号：US13313364
申请日：2011-12-07
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G11C29/42 , G06F11/10 , G11C29/54 , G11C29/04
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.
摘要翻译：提供了用于在系统存储器内有效存储元位的机制。这些机制将L / G位和SUE位组合以形成元位。机制然后在第一个数据周期上确定高速缓存行的本地/全局状态。这些机制将数据转发到请求的高速缓存，并且请求高速缓存可以基于高速缓存行的本地/全局状态全局重新发出请求。这些机制然后在数据的第二个或随后的周期中确定高速缓存行的特殊的不可校正错误状态。机制执行错误处理，而不管请求是否在全球重新发布。

10. 发明申请

US20130339821A1 THREE DIMENSIONAL(3D) MEMORY DEVICE SPARING 有权
标题翻译：三维（3D）存储器件分配
公开(公告)号：US20130339821A1
公开(公告)日：2013-12-19
申请号：US13523195
申请日：2012-06-14
申请人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
发明人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11C29/4401 , G06F11/1048 , G06F11/1072 , G06F11/1666 , G06F11/20 , G11C7/24 , G11C29/70 , G11C29/83 , G11C2029/0411 , H03M13/05
摘要： According to one embodiment of the present invention, a method for bank sparing in a 3D memory device that includes detecting, by a memory controller, a first error in the 3D memory device and detecting a second error in a first element in a first rank of the 3D memory device, wherein the first element in the first rank has an associated first chip select. The method also includes sending a command to the 3D memory device to set mode registers in a master logic portion of the 3D memory device that enable a second element to receive communications directed to the first element and wherein the second element is in a second rank of the 3D memory device, wherein the first element and second element are each either a bank or a bank group that comprise a plurality of chips.
摘要翻译：根据本发明的一个实施例，一种用于在三维存储器件中进行库保存的方法，该方法包括由存储器控制器检测3D存储器件中的第一个误差并检测第一个等级的第一个元件中的第二个误差 3D存储器件，其中第一级中的第一元件具有相关联的第一片选。该方法还包括向3D存储器设备发送命令以设置3D存储器件的主逻辑部分中的模式寄存器，其使得第二元件能够接收指向第一元件的通信，并且其中第二元件处于第二等级 3D存储器件，其中第一元件和第二元件各自是包括多个芯片的存储体或存储体组。

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