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1. 发明授权

US07188274B2 Memory repair analysis method and circuit 失效
标题翻译：记忆修复分析方法和电路
公开(公告)号：US07188274B2
公开(公告)日：2007-03-06
申请号：US10774512
申请日：2004-02-10
申请人： Benoit Nadeau-Dostie , Robert A. Abbott
发明人： Benoit Nadeau-Dostie , Robert A. Abbott
IPC分类号： G06F11/00
CPC分类号： G11C29/4401 , G11C29/44 , G11C29/72
摘要： A method and circuit for repairing a memory array having one or more memory segments each having one spare column and a predetermined number of spare rows common to all segments, the method comprises, while testing the memory array for failures, generating an equal number of unique segment repair solutions for each segment with each segment repair solution including one defective column address, if any, and a number of defective row addresses, if any, corresponding to the predetermined number of spare rows; and, after completing testing, analyzing all segment repair solution combinations consisting of one segment repair solution selected from each segment; and identifying the best segment repair solution combination of combinations having a number of different defective row addresses which is less than or equal to the predetermined number of spare rows.
摘要翻译：一种用于修复具有一个或多个存储器段的存储器阵列的方法和电路，每个存储器段具有一个备用列和预定数量的所有段公用的备用行，该方法包括在测试存储器阵列以获得故障时产生相等数量的唯一每个段的段修复解决方案，其中每个段修复解决方案包括与预定数量的备用行相对应的一个缺陷列地址（如果有的话）和若干有缺陷的行地址（如果有的话）; 在完成测试后，分析由每个部分选择的一个部分修复解决方案组成的所有段修复解决方案组合; 以及识别具有小于或等于预定数量的备用行的具有多个不同缺陷行地址的组合的最佳段修复方案组合。

2. 发明申请

US20050240847A1 Clock controller for at-speed testing of scan circuits 有权
标题翻译：时钟控制器，用于扫描电路的高速测试
公开(公告)号：US20050240847A1
公开(公告)日：2005-10-27
申请号：US11013319
申请日：2004-12-17
申请人： Benoit Nadeau-Dostie , Jean-Francois Cote
发明人： Benoit Nadeau-Dostie , Jean-Francois Cote
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319
CPC分类号： G01R31/31858 , G01R31/318552 , G01R31/31922
摘要： A test clock controller for generating a test clock signal for scan chains in integrated circuits having one or more clock domains, comprises a shift clock controller for generating a shift clock signal for use in loading test patterns into scan chains in the clock domains and for unloading a test response patterns from the scan chains and for generating a burst phase signal after loading a test pattern; and a burst clock controller associated with each of one or more clock domains and responsive to a burst phase signal for generating a burst of clock pulses derived from a respective reference clocks and including a first group of burst clock pulses having a selected reduced frequency relative to the reference clock and a second group of burst clock pulses having a frequency corresponding to that of the reference clock.
摘要翻译：一种测试时钟控制器，用于在具有一个或多个时钟域的集成电路中产生用于扫描链的测试时钟信号，包括移位时钟控制器，用于产生用于将测试模式加载到时钟域中的扫描链中并用于卸载的移位时钟信号来自扫描链的测试响应模式并且用于在加载测试模式之后产生突发相位信号; 以及突发时钟控制器，其与一个或多个时钟域中的每一个相关联，并且响应于脉冲串相位信号，用于产生从各个参考时钟导出的时钟脉冲串，并且包括相对于相对参考时钟具有选定的降低的频率的第一组脉冲串时钟脉冲参考时钟和具有与参考时钟的频率对应的频率的第二组突发时钟脉冲。

3. 发明授权

US06760874B2 Test access circuit and method of accessing embedded test controllers in integrated circuit modules 有权
标题翻译：测试访问电路和集成电路模块中访问嵌入式测试控制器的方法
公开(公告)号：US06760874B2
公开(公告)日：2004-07-06
申请号：US10139294
申请日：2002-05-07
申请人： Jean-François Côté , Benoit Nadeau-Dostie
发明人： Jean-François Côté , Benoit Nadeau-Dostie
IPC分类号： G01R3128
CPC分类号： G01R31/318558 , G01R31/31724 , G01R31/318555
摘要： A test access circuit (TAC) for use in controlling test resources including child test access circuits (TACs) and/or test controllers, in an integrated circuit, comprises an enable input for enabling or disabling access to the test resources, a test port associated with each test resource, each test port including a test port enable output for connection to an enable input of an associated test resource; and an input for receiving a serial output of the associated test resource; and a selector for selecting a test resource for communication therewith.
摘要翻译：在集成电路中用于控制测试资源（包括子测试访问电路（TAC）和/或测试控制器）的测试访问电路（TAC）包括用于启用或禁用对测试资源的访问的启用输入，对于每个测试资源，每个测试端口包括用于连接到相关测试资源的使能输入的测试端口使能输出; 以及用于接收相关测试资源的串行输出的输入; 以及用于选择用于与之通信的测试资源的选择器。

4. 发明授权

US06738938B2 Method for collecting failure information for a memory using an embedded test controller 有权
标题翻译：使用嵌入式测试控制器收集存储器故障信息的方法
公开(公告)号：US06738938B2
公开(公告)日：2004-05-18
申请号：US10156117
申请日：2002-05-29
申请人： Benoit Nadeau-Dostie , Jean-François Côté
发明人： Benoit Nadeau-Dostie , Jean-François Côté
IPC分类号： G11C2900
CPC分类号： G11C29/44
摘要： A method of collecting failure information when testing a memory comprises performing a test of the memory according to a test algorithm, and, while performing the test, counting failure events which occur after a predetermined number of masked events; stopping the test upon occurrence of a stopping criterion which comprises one of occurrence of a first failure event, a change of a test operation; a change of a memory column address; a change of a memory row address; a change of a memory bank address; and a change of a test algorithm phase; and storing failure information.
摘要翻译：在测试存储器时收集故障信息的方法包括根据测试算法对存储器进行测试，并且在执行测试的同时，计算在预定数量的屏蔽事件之后发生的故障事件; 在出现停止标准时停止测试，其包括发生第一故障事件，测试操作的改变之一; 更改内存列地址; 更改内存行地址; 更改存储库地址; 并改变测试算法阶段; 并存储故障信息。

5. 发明授权

US06671839B1 Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith 有权
标题翻译：扫描测试方法，用于提供故障测试模式的实时识别和与其一起使用的测试双控制器
公开(公告)号：US06671839B1
公开(公告)日：2003-12-30
申请号：US10180116
申请日：2002-06-27
申请人： Jean-François Côté , Benoit Nadeau-Dostie
发明人： Jean-François Côté , Benoit Nadeau-Dostie
IPC分类号： G01R3128
CPC分类号： G01R31/318563 , G01R31/318555 , G01R31/318566 , G06F2201/83
摘要： A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern comprises performing a number of test operations and storing a test response signature corresponding to each block of test patterns into a signature register; replacing the test response signature in the signature register with a test block expected signature; identifying the block as a failing test block when the test response signature is different from the test block expected signature; and repeating preceding steps until the test is complete.
摘要翻译：一种对集成电路进行扫描测试以提供具有至少一个故障测试模式的测试模式块的实时识别的方法包括执行多个测试操作并将对应于每个测试模式块的测试响应签名存储到签名寄存器 ; 用测试块预期签名代替签名寄存器中的测试响应签名; 当测试响应签名与测试块预期签名不同时，将块识别为失败的测试块; 并重复前面的步骤，直到测试完成。

6. 发明授权

US06614263B2 Method and circuitry for controlling clocks of embedded blocks during logic bist test mode 有权
标题翻译：用于在逻辑双工测试模式下控制嵌入式块的时钟的方法和电路
公开(公告)号：US06614263B2
公开(公告)日：2003-09-02
申请号：US10125384
申请日：2002-04-19
申请人： Benoit Nadeau-Dostie , Jean-Francois Côté
发明人： Benoit Nadeau-Dostie , Jean-Francois Côté
IPC分类号： H03K1900
CPC分类号： G01R31/3187
摘要： One aspect of the invention is generally defined as a method of designing an integrated circuit for distributing test clock signals to embedded cores having at least one core functional clock input, the method comprising, for each core, providing a clock gating circuit for selectively disabling a core functional clock signal applied to a core primary clock input; and providing a core clock selection circuit for each secondary core functional clock input for selecting one of a core functional clock signal output by the gating circuit and a core test clock signal and applying a selected signal to the each secondary core functional clock input.
摘要翻译：本发明的一个方面通常定义为设计用于将测试时钟信号分配给具有至少一个核心功能时钟输入的嵌入式核心的集成电路的方法，所述方法包括：为每个核心提供时钟选通电路，用于选择性地禁用核心功能时钟信号施加到核心主时钟输入; 以及提供用于每个次级核心功能时钟输入的核心时钟选择电路，用于选择门控电路输出的核心功能时钟信号和核心测试时钟信号之一，并将所选择的信号应用于每个次级核心功能时钟输入。

7. 发明授权

US06487688B1 Method for testing circuits with tri-state drivers and circuit for use therewith 有权
标题翻译：用于测试具有三态驱动器的电路的方法和与其一起使用的电路
公开(公告)号：US06487688B1
公开(公告)日：2002-11-26
申请号：US09472386
申请日：1999-12-23
申请人： Benoit Nadeau-Dostie
发明人： Benoit Nadeau-Dostie
IPC分类号： G01R3128
CPC分类号： G01R31/318558
摘要： A scan-testing method for circuits having tri-state bus drivers disables all drivers during scan intervals and enables at most one of the bus drivers during the capture interval. A driver select signal is generated for each bus driver and gated with a corresponding circuit functional enable signal to generate a driver enable signal. A driver is selected by loading a driver select code into memory elements during the scan-in sequence and decoding the driver select code to produce the driver select signals.
摘要翻译：具有三态总线驱动器的电路的扫描测试方法在扫描间隔期间禁用所有驱动器，并且在捕获间隔期间最多允许一个总线驱动器。为每个总线驱动器生成一个驱动器选择信号，并与相应的电路功能使能信号相加，以产生一个驱动器使能信号。通过在扫描顺序期间将驱动器选择代码加载到存储器元件中并且解码驱动器选择代码以产生驱动器选择信号来选择驱动器。

8. 发明授权

US6000051A Method and apparatus for high-speed interconnect testing 失效
标题翻译：高速互连测试的方法和装置
公开(公告)号：US6000051A
公开(公告)日：1999-12-07
申请号：US948842
申请日：1997-10-10
申请人： Benoit Nadeau-Dostie , Jean-Francois Cote
发明人： Benoit Nadeau-Dostie , Jean-Francois Cote
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/31855
摘要： A method of testing high speed interconnectivity of circuit boards having components operable at a high speed system clock, employing an IEEE 1149.1 standard test method in which test data is shifted into and from the components at the rate of a test clock during Shift.sub.-- In and Shift.sub.-- Out operations, and having an Update operation and a Capture operation between the Shift.sub.-- In and Shift.sub.-- Out operations, the components including a first group of components capable of performing the Update and Capture operations at the rate of the Test Clock only and a second group of components capable of performing the Update and Capture operations at the rate of the system clock, the method comprising the steps of performing the Shift.sub.-- In operation in all of the components concurrently at the rate of the Test Clock; performing the Update and Capture Operations in the first group of components at the rate of the Test Clock; and performing the Update and Capture Operations in the second group of components at the rate of the system Clock. The method employs a novel integrated circuit, test controller and boundary scan cells.
摘要翻译：一种测试具有可在高速系统时钟操作的部件的电路板的高速互连性的方法，采用IEEE 1149.1标准测试方法，其中测试数据在Shift-In期间以测试时钟的速率被移入和移出部件， Shift-Out操作，并且在Shift-In和Shift-Out操作之间具有Update操作和Capture操作，这些组件包括能够以仅测试时钟的速率执行Update和Capture操作的第一组组件，以及能够以系统时钟的速率执行更新和捕获操作的第二组组件，所述方法包括以所述测试时钟的速率同时在所有组件中执行所述移位操作的步骤; 以测试时钟的速率在第一组组件中执行更新和捕获操作; 并以系统时钟的速率在第二组组件中执行更新和捕获操作。该方法采用新颖的集成电路，测试控制器和边界扫描单元。

9. 发明授权

US5812469A Method and apparatus for testing multi-port memory 失效
标题翻译：用于测试多端口存储器的方法和装置
公开(公告)号：US5812469A
公开(公告)日：1998-09-22
申请号：US775856
申请日：1996-12-31
申请人： Benoit Nadeau-Dostie , Jean-Francois Cote
发明人： Benoit Nadeau-Dostie , Jean-Francois Cote
IPC分类号： G11C8/16 , G11C29/28 , G11C7/00
CPC分类号： G11C29/28 , G11C8/16
摘要： A method of and apparatus for testing multi-port memory performs a shadow read to an adjacent memory cell concurrent with a write operation associated with typical read-write testing. In the presence of a bit wire short or a word wire short, the concurrent read of an adjacent memory cell will cause the value of that cell to be corrupted. The corrupted value is then found by the read-write testing. Consequently, the testing takes no longer than read-write testing. In addition, the testing scheme can be modified for memory with read only ports. An embodiment of the apparatus employs an exclusive OR gate on the least significant bit of the test row address line to generate the shadow read address.
摘要翻译：用于测试多端口存储器的方法和装置对与典型读写测试相关联的写操作同时执行对相邻存储器单元的影子读取。在有线短路或字线短路的情况下，相邻存储单元的并发读取将导致该单元的值被破坏。然后通过读写测试发现损坏的值。因此，测试不再需要读写测试。此外，可以使用只读端口对存储器修改测试方案。该装置的实施例在测试行地址线的最低有效位上采用异或门来产生影子读取地址。

10. 发明授权

US08683280B2 Test generator for low power built-in self-test 有权
标题翻译：用于低功率内置自检的发电机
公开(公告)号：US08683280B2
公开(公告)日：2014-03-25
申请号：US13451527
申请日：2012-04-19
申请人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Benoit Nadeau-Dostie
发明人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Benoit Nadeau-Dostie
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318575 , G01R31/31721 , G01R31/318385 , G01R31/3187
摘要： Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle control data based on bit sequence data generated by the pseudo-random pattern generator unit, and a hold register unit configured to generate low power test pattern data by replacing, based on the toggle control data received from the toggle control unit, data from some or all of outputs of the pseudo-random pattern generator unit with constant values during various time periods. The low power test generator may further comprise a phase shifter configured to combine bits of the low power test pattern data for driving scan chains.
摘要翻译：本发明的方面涉及基于BIST的低功率测试。低功率测试发生器可以包括伪随机模式发生器单元，触发控制单元，被配置为基于由伪随机模式发生器单元生成的比特序列数据产生切换控制数据;以及保持寄存器单元，被配置为产生低功率测试图案数据通过基于从触发控制单元接收到的切换控制数据，在各种时间段期间以常数值替换来自伪随机模式发生器单元的一些或全部输出的数据。低功率测试发生器还可以包括移相器，其被配置为组合用于驱动扫描链的低功率测试图案数据的位。

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