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1. 发明授权

US08555050B2 Apparatus and method thereof for reliable booting from NAND flash memory 失效
标题翻译：用于从NAND闪存可靠引导的装置及其方法
公开(公告)号：US08555050B2
公开(公告)日：2013-10-08
申请号：US12836962
申请日：2010-07-15
申请人： Boaz Shahar , Dan Beygelman , Oren Wolach
发明人： Boaz Shahar , Dan Beygelman , Oren Wolach
IPC分类号： G06F9/00 , G06F9/24 , G06F12/00
CPC分类号： G06F9/4401
摘要： An apparatus for enabling booting from a NAND flash memory comprises a NAND flash controller connected to the NAND flash memory, wherein the NAND flash memory is configured to include at least a starter section for storing boot code, the starter section includes a predefined number of blocks to store copies of the boot code duplicated in a configurable number of blocks; and a fetch emulator for fetching a valid and complete starter block that includes the boot code.
摘要翻译：一种用于启动从NAND闪速存储器引导的装置，包括连接到NAND闪速存储器的NAND闪存控制器，其中NAND闪速存储器被配置为至少包括用于存储引导代码的起动器部分，起动器部分包括预定数量的块存储复制在可配置数量块中的引导代码的副本; 以及一个获取模拟器，用于获取包含引导代码的有效且完整的启动器块。

2. 发明授权

US07986697B2 Method for processing information fragments and a device having information fragment processing capabilities 有权
标题翻译：用于处理信息片段的方法和具有信息片段处理能力的装置
公开(公告)号：US07986697B2
公开(公告)日：2011-07-26
申请号：US12304187
申请日：2006-06-13
申请人： Boaz Shahar , Liat Kochavi , Noam Sheffer , Michal Shmueli
发明人： Boaz Shahar , Liat Kochavi , Noam Sheffer , Michal Shmueli
IPC分类号： H04L12/28
CPC分类号： H04L47/10 , H04L47/34 , H04L49/90 , H04L49/9094
摘要： A device and method for processing information fragments, the method includes: receiving multiple information fragments from multiple communication paths; wherein the each information fragment is associated with a cyclic serial number indicating of a generation time of the information fragment; storing the multiple information fragments in multiple input queues, each input queue being associated with a communication path out of the multiple communication paths; determining whether at least one serial number associated with at least one valid information fragment positioned in a head of one of the multiple input queues is located within a pre-rollout serial number range; mapping, in response to the determination, serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues to at least one serial number range that differs from the pre-rollout serial number range; and sending to an output queue information fragment metadata associated with a minimal valued serial number out of the serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues.
摘要翻译：一种用于处理信息片段的装置和方法，所述方法包括：从多个通信路径接收多个信息片段; 其中每个信息片段与指示信息片段的生成时间的循环序列号相关联; 将多个信息片段存储在多个输入队列中，每个输入队列与多个通信路径中的通信路径相关联; 确定与位于多个输入队列之一的头部中的至少一个有效信息片段相关联的至少一个序列号是否位于预先卷入序列号范围内; 响应于所述确定，将与位于所述多个输入队列的头部中的每个有效信息片段相关联的序列号映射到与所述预先推出序列号范围不同的至少一个序列号范围; 并且将与位于多个输入队列的头部中的每个有效信息片段相关联的序列号中的最小值序列号相关联的数据发送到输出队列信息片段。

3. 发明申请

US20080198866A1 Hybrid Method and Device for Transmitting Packets 有权
标题翻译：用于传输数据包的混合方法和设备
公开(公告)号：US20080198866A1
公开(公告)日：2008-08-21
申请号：US11916711
申请日：2005-06-07
申请人： Boaz Shahar , Freddy Gabbay , Eyal Soha
发明人： Boaz Shahar , Freddy Gabbay , Eyal Soha
IPC分类号： H04L12/56
CPC分类号： H04L12/5693 , H04L47/245 , H04L47/50 , H04L47/522 , H04L47/58 , H04L47/6235
摘要： A method for transmitting packets, the method includes receiving multiple packets at multiple queues. The method is characterized by dynamically defining fixed priority queues and weighted fair queuing queues, and scheduling a transmission of packets in response to a status of the multiple queues and in response to the definition. A device for transmitting packets, the device includes multiple queues adapted to receive multiple packets. The device includes a circuit that is adapted to dynamically define fixed priority queues and weighted fair queuing queues out of the multiple queues and to schedule a transmission of packets in response to a status of the multiple queues and in response to the definition.
摘要翻译：一种用于发送分组的方法，所述方法包括在多个队列处接收多个分组。该方法的特征在于动态地定义固定优先级队列和加权公平排队队列，并且响应于多个队列的状态并响应于定义来调度分组的传输。一种用于传输分组的设备，该设备包括适于接收多个分组的多个队列。该设备包括适于在多个队列中动态地定义固定优先级队列和加权公平排队队列的电路，并响应于该定义响应于多个队列的状态来调度分组的传输。

4. 发明申请

US20060153116A1 Error correction of balanced codeword sequence 失效
标题翻译：平衡码字序列的纠错
公开(公告)号：US20060153116A1
公开(公告)日：2006-07-13
申请号：US10499236
申请日：2002-12-17
申请人： Eyran Lida , Boaz Shahar
发明人： Eyran Lida , Boaz Shahar
IPC分类号： G06F11/00 , H04J3/08 , H04B7/14
CPC分类号： H04L7/0338 , H03M13/31 , H04L1/0026 , H04L1/0045 , H04L25/14 , H04L25/4908
摘要： A method for recoding an input sequence of words, including assigning a respective bit-grade such as a reliability valve depending on sampling phases to at least one of the bits in a first word in the input sequence, deriving candidate words (161, W1, W2) from the first word in response to the respective bit-grade, and inserting one of the candidate words into each of a plurality of candidate sequences (T1, T2, T3), so that each of the candidate sequences contains one of the candidate words. The method further includes adding subsequent words (Wx(t), Wx(t−1), . . . ) to the candidate sequences, the subsequent words consisting of a further candidate word derived from a further word in the input sequence, computing respective sequence parameters for the candidate sequences, based on a relation between the candidate words and the subsequent words in the candidate sequences involving the digital sum variation, selecting one of die candidate sequences (T1) in response to the sequence parameters, and outputting one of the candidate words contained in the selected candidate sequence. For gigabit ethernet using a 8b/10b coding scheme.
摘要翻译：一种用于对输入序列进行重新编码的方法，包括根据采样相位将诸如可靠性阀的相应比特等级分配给输入序列中的第一个字中的至少一个比特，导出候选词（161，W 1 ，W 2），并且将候选词中的一个插入到多个候选序列（T 1，T 2，T 3）中的每一个中，使得每个候选序列包含候选词之一。该方法还包括将后续字（Wx（t），Wx（t-1），...）添加到候选序列，后续字由由输入序列中的另一个字导出的另外的候选词组成，基于涉及数字和变化的候选序列中的候选字与后续字之间的关系，候选序列的序列参数，响应于序列参数选择一个候选序列（T 1），并输出其中之一包含在所选候选序列中的候选词。对于千兆以太网使用8b / 10b编码方案。

5. 发明授权

US06891846B2 Method and apparatus for a traffic shaper 有权
标题翻译：交通整形机的方法和装置
公开(公告)号：US06891846B2
公开(公告)日：2005-05-10
申请号：US09884377
申请日：2001-06-18
申请人： Boaz Shahar , Stefania Gandal , Aviram Hertzberg , David Sitbon
发明人： Boaz Shahar , Stefania Gandal , Aviram Hertzberg , David Sitbon
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/54
CPC分类号： H04Q11/0478 , H04L2012/5651 , H04L2012/5672 , H04L2012/5679 , H04L2012/568 , H04L2012/5682
摘要： Packets of data from multiple queues are transferred onto a single channel. Each queue has associated with it a data rate for servicing a packet within the queue. Each queue has an integer that, relative to the other numbers, represents is inversely related to the assigned data rate. Each queue has associated with it a counter and that is loaded with its corresponding integer. The counter values are compared, and the queue corresponding to the lowest counter value has a packet coupled to the channel. The counter of the selected queue is incremented by its integer. The next queue that is selected is the one that corresponds to the counter with the lowest count value after the counter that corresponds to the previously selected queue has been updated.
摘要翻译：来自多个队列的数据包将传输到单个通道。每个队列都与它相关联一个用于服务队列内的数据包的数据速率。每个队列具有相对于其他数字表示与分配的数据速率成反比关系的整数。每个队列与它相关联一个计数器，并加载其对应的整数。比较计数器值，对应于最低计数器值的队列具有耦合到该通道的分组。所选队列的计数器增加其整数。所选择的下一个队列是对应于具有最低计数值的计数器的计数器，对应于先前选择的队列的计数器已被更新。

6. 发明申请

US20120017071A1 Apparatus and Method Thereof for Reliable Booting from NAND Flash Memory 失效
标题翻译：从NAND闪存可靠引导的设备及方法
公开(公告)号：US20120017071A1
公开(公告)日：2012-01-19
申请号：US12836962
申请日：2010-07-15
申请人： Boaz Shahar , Dan Beygelman , Oren Wolach
发明人： Boaz Shahar , Dan Beygelman , Oren Wolach
IPC分类号： G06F9/00
CPC分类号： G06F9/4401
摘要： An apparatus for enabling booting from a NAND flash memory comprises a NAND flash controller connected to the NAND flash memory, wherein the NAND flasher memory is configured to include at least a starter section for storing boot code, the starter section includes a predefined number of blocks to store copies of the boot code duplicated in a configurable number of blocks; and a fetch emulator for fetching a valid and complete starter block that includes the boot code.
摘要翻译：一种用于启动从NAND闪速存储器引导的装置包括连接到NAND闪速存储器的NAND闪存控制器，其中NAND闪存器存储器被配置为至少包括用于存储引导代码的起动器部分，起动器部分包括预定数量的块存储复制在可配置数量块中的引导代码的副本; 以及一个获取模拟器，用于获取包含引导代码的有效且完整的启动器块。

7. 发明授权

US07257169B2 Deserializer 有权
标题翻译：解串器
公开(公告)号：US07257169B2
公开(公告)日：2007-08-14
申请号：US10320774
申请日：2002-12-16
申请人： Boaz Shahar , Eyran Lida , Eyal Massad
发明人： Boaz Shahar , Eyran Lida , Eyal Massad
IPC分类号： H03D1/00
CPC分类号： H04L7/0338 , H03M13/31 , H04L1/0026 , H04L1/0045 , H04L25/14 , H04L25/4908
摘要： A receiver for deserializing a stream of data bits, including a single clock which is adapted to generate a first plurality of clock phases, and a sample generator which is adapted to sample the stream so as to generate initial data values of each of the bits at times defined by the first plurality of clock phases.The receiver further includes digital circuitry which is adapted to group the initial values into a second plurality of sampling phase sets, according to the clock phases at which the values were sampled, and assign each of the phase sets a respective grade in response to at least some of the initial values. The circuitry selects a decoding phase set from the phase sets in response to the respective grades, and decodes the stream in response to initial values of the decoding phase set to generate decoded values of the consecutive bits.
摘要翻译：一种用于反序列化数据比特流的接收机，包括适于产生第一多个时钟相位的单个时钟，以及适于对该流进行采样以便生成每个比特的初始数据值的采样发生器时间由第一多个时钟相位定义。接收机还包括数字电路，其适于根据采样值的时钟相位将初始值分组为第二多个采样相位集合，并且响应于至少对每个相位集合分配相应的等级一些初始值。该电路根据相应的等级从相位集合中选择解码相位集合，并且响应于设置的解码相位的初始值对该流进行解码以生成连续比特的解码值。

8. 发明授权

US5740180A Circuit and test method for testing input cells 失效
标题翻译：用于测试输入单元的电路和测试方法
公开(公告)号：US5740180A
公开(公告)日：1998-04-14
申请号：US801451
申请日：1997-02-18
申请人： Udi Barel , Boaz Shahar , Ido Reuveny
发明人： Udi Barel , Boaz Shahar , Ido Reuveny
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04
CPC分类号： G01R31/2884
摘要： A circuit (100) comprises a built-in test circuit (150) which verifies the proper operation of input cells (130) when they receive signals at a first level (71) and at a second level (72). The test circuit (160) comprises a first and a second logic (110, 120) which receive power only when a test is performed. Thereby power consumption of the test circuit (160) is reduced. The first and the second logic (110, 120) are conveniently formed by a combination of parallel coupled transistors acting in an logical OR-function.
摘要翻译：电路（100）包括内置的测试电路（150），当它们在第一电平（71）和第二电平（72）接收信号时，验证输入单元（130）的适当操作。测试电路（160）包括仅在执行测试时才接收功率的第一和第二逻辑（110,120）。由此，测试电路（160）的功耗降低。第一和第二逻辑（110,120）通过以逻辑或函数作用的并联耦合晶体管的组合方便地形成。

9. 发明申请

US20090323710A1 METHOD FOR PROCESSING INFORMATION FRAGMENTS AND A DEVICE HAVING INFORMATION FRAGMENT PROCESSING CAPABILITIES 有权
标题翻译：处理信息片段的方法和具有信息片段处理能力的装置
公开(公告)号：US20090323710A1
公开(公告)日：2009-12-31
申请号：US12304187
申请日：2006-06-13
申请人： Boaz Shahar , Liat Kochavi , Noam Sheffer , Michal Shmueli
发明人： Boaz Shahar , Liat Kochavi , Noam Sheffer , Michal Shmueli
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/34 , H04L49/90 , H04L49/9094
摘要： A device and method for processing information fragments, the method includes: receiving multiple information fragments from multiple communication paths; wherein the each information fragment is associated with a cyclic serial number indicating of a generation time of the information fragment; storing the multiple information fragments in multiple input queues, each input queue being associated with a communication path out of the multiple communication paths; determining whether at least one serial number associated with at least one valid information fragment positioned in a head of one of the multiple input queues is located within a pre-rollout serial number range; mapping, in response to the determination, serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues to at least one serial number range that differs from the pre-rollout serial number range; and sending to an output queue information fragment metadata associated with a minimal valued serial number out of the serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues.
摘要翻译：一种用于处理信息片段的装置和方法，所述方法包括：从多个通信路径接收多个信息片段; 其中每个信息片段与指示信息片段的生成时间的循环序列号相关联; 将多个信息片段存储在多个输入队列中，每个输入队列与多个通信路径中的通信路径相关联; 确定与位于多个输入队列之一的头部中的至少一个有效信息片段相关联的至少一个序列号是否位于预先卷入序列号范围内; 响应于所述确定，将与位于所述多个输入队列的头部中的每个有效信息片段相关联的序列号映射到与所述预先推出序列号范围不同的至少一个序列号范围; 并且将与位于多个输入队列的头部中的每个有效信息片段相关联的序列号中的最小值序列号相关联的数据发送到输出队列信息片段。

10. 发明授权

US5438670A Method of prechecking the validity of a write access request 失效
标题翻译：预读写访问请求的有效性的方法
公开(公告)号：US5438670A
公开(公告)日：1995-08-01
申请号：US84316
申请日：1993-06-25
申请人： Gigi Baror , Moti Beck , Dan Biran , Elliot Cohen , Yair Hadas , Benny Konstantin , Jonanthan Levy , Reuven Marko , Aharon Ostrer , Rami Saban , Alon Shackam , Boaz Shahar
发明人： Gigi Baror , Moti Beck , Dan Biran , Elliot Cohen , Yair Hadas , Benny Konstantin , Jonanthan Levy , Reuven Marko , Aharon Ostrer , Rami Saban , Alon Shackam , Boaz Shahar
IPC分类号： G06F9/38 , G06F12/08 , G06F12/10 , G06F15/78 , G06F12/00
CPC分类号： G06F9/3802 , G06F12/0848 , G06F12/1054 , G06F15/7832
摘要： A method and apparatus for prechecking (probing) the validity of an access request for writing result data to an external system prior to executing the instruction that generates the result is provided. This allows instruction execution to continue uninterrupted in the event that the write is allowed. The microprocessor's Address Unit issues a "probe" request to the Memory Management Unit (MMU) via an internal bus while saving the instruction's virtual address in a virtual address buffer local to the Address Unit. The MMU checks the validity of the "probe" request without converting the virtual address to a physical address and issues an access grant signal which is saved by the microprocessor's Execution Unit for subsequent use. The Execution Unit processes the data in parallel to the MMU checking the validity of the probe request. If the virtual address associated with the probe request resulted in an access grant signal, then the Execution Unit issues a write request while the virtual address previously stored in the Address Unit is sent to the MMU for translation to a physical address. Both the write data and the physical address are stored in a buffer in the microprocessor's Bus Interface Unit (BIU) for subsequent transfer to an external system. The data is then written to the external system at the physical address provided by the BIU.
摘要翻译：提供了一种用于在执行生成结果的指令之前预先检查（探测）用于将结果数据写入外部系统的访问请求的有效性的方法和装置。这允许指令执行在允许写入的情况下不间断地继续。微处理器的地址单元通过内部总线向存储器管理单元（MMU）发出“探测”请求，同时将指令的虚拟地址保存在地址单元本地的虚拟地址缓冲区中。 MMU检查“探测”请求的有效性，而不将虚拟地址转换为物理地址，并发出由微处理器的执行单元保存以供后续使用的访问许可信号。执行单元与MMU并行处理数据，检查探测请求的有效性。如果与探测请求相关联的虚拟地址导致访问许可信号，则执行单元发出写请求，而将先前存储在地址单元中的虚拟地址发送到MMU以转换为物理地址。写入数据和物理地址都存储在微处理器总线接口单元（BIU）中的缓冲器中，以便后续传输到外部系统。然后将数据以BIU提供的物理地址写入外部系统。

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