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1. 发明授权

US08400863B1 Configurable memory block 有权
标题翻译：可配置的内存块
公开(公告)号：US08400863B1
公开(公告)日：2013-03-19
申请号：US12860734
申请日：2010-08-20
申请人： Zun Yang Tan , Wei Yee Koay , Boon Jin Ang , Tat Mun Lui , Eu Geen Chew
发明人： Zun Yang Tan , Wei Yee Koay , Boon Jin Ang , Tat Mun Lui , Eu Geen Chew
IPC分类号： G11C8/00
CPC分类号： G11C8/12
摘要： Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second memory block to form an array of memory blocks. Each of the memory blocks has multiple bit lines with a dedicated address decoder coupled to the bit lines from each of the memory blocks. Switches are placed in between the first and second memory blocks such that each of the bit lines from the first memory block is connected to a corresponding bitline from the second memory block through one of the switches. The switches may be used to either connect the second memory block to the first memory block or disconnect the second memory block from the first memory block.
摘要翻译：公开了用于存储器阵列的电路和操作可配置存储器块的方法。所公开的存储器电路的实施例包括耦合到第二存储器块以形成存储器块阵列的第一存储器块。每个存储器块具有多个位线，其中专用地址解码器耦合到来自每个存储器块的位线。开关被放置在第一和第二存储器块之间，使得来自第一存储器块的每个位线通过其中一个开关连接到来自第二存储器块的相应位线。交换机可以用于将第二存储器块连接到第一存储器块或将第二存储器块与第一存储器块断开。

2. 发明申请

US20100061166A1 DYNAMIC REAL-TIME DELAY CHARACTERIZATION AND CONFIGURATION 有权
标题翻译：动态实时延迟特征和配置
公开(公告)号：US20100061166A1
公开(公告)日：2010-03-11
申请号：US12208967
申请日：2008-09-11
申请人： Jun Pin Tan , Wei Yee Koay , Boon Jin Ang , Choong Kit Wong , Guang Sheng Soh
发明人： Jun Pin Tan , Wei Yee Koay , Boon Jin Ang , Choong Kit Wong , Guang Sheng Soh
IPC分类号： G11C7/00 , H03K19/173
CPC分类号： H03K19/1735 , G11C29/02 , G11C29/023 , G11C29/028 , H03K5/133
摘要： In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.
摘要翻译：在掩模可编程集成电路（例如结构化ASIC）中，延迟链提供由掩模可编程开关设置的延迟。延迟链接收输入以允许使用JTAG控制器覆盖延迟掩码编程的延迟。这允许测试不同的延迟。输入也可以由熔丝块提供，使得熔丝块可以覆盖掩模可编程开关，从而允许在掩模编程之后改变延迟。

3. 发明授权

US07242218B2 Techniques for combining volatile and non-volatile programmable logic on an integrated circuit 有权
标题翻译：在集成电路上组合易失性和非易失性可编程逻辑的技术
公开(公告)号：US07242218B2
公开(公告)日：2007-07-10
申请号：US11003586
申请日：2004-12-02
申请人： Rafael Camarota , Irfan Rahim , Boon Jin Ang , Thow Pang Chong
发明人： Rafael Camarota , Irfan Rahim , Boon Jin Ang , Thow Pang Chong
IPC分类号： H03K19/173 , H03K19/177 , G06F7/38 , H01L25/00
CPC分类号： G06F15/7867 , H03K19/17732 , H03K19/1776 , H03K19/17768 , H03K19/17772 , H03K19/17776
摘要： Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. The non-volatile memory can also provide security features to a user design, such as encryption.
摘要翻译：提供了将易失性和非易失性可编程逻辑组合到一个集成电路（IC）中的技术。 IC分为两部分。可编程逻辑的第一块由存储在片上非易失性存储器中的位来配置。可编程逻辑的第二块由存储在片外存储器中的位配置。 IC上的IO组的功能在IC的两个逻辑块之间复用。第一块中的可编程逻辑可以在可配置第二块中的可编程逻辑的几分之一时间内配置和完全运行。第一块中的可编程逻辑可以配置得足够快，并具有足够的独立性来辅助第二块的配置。非易失性存储器还可以为诸如加密的用户设计提供安全特征。

4. 发明授权

US06489817B1 Clock divider using positive and negative edge triggered state machines 有权
标题翻译：时钟分频器使用正和负边缘触发状态机
公开(公告)号：US06489817B1
公开(公告)日：2002-12-03
申请号：US09965290
申请日：2001-09-26
申请人： Choong Kit Wong , Sammy Cheung , Boon Jin Ang
发明人： Choong Kit Wong , Sammy Cheung , Boon Jin Ang
IPC分类号： H03K2100
CPC分类号： H03K23/68
摘要： A clock divider is described. The clock divider includes: a positive edge triggered state machine having a first input for receiving a first input signal and a first output for providing a first output signal; a negative edge triggered state machine having a second input for receiving a second input signal and a second output for providing a second output signal; and a first combination logic coupled to the positive edge triggered state machine and the negative edge triggered state machine, the first combination logic having a third input for receiving third input signals and a third output for providing a third output signal, where (1) at least one of the first input signal and the second input signal includes an input clock signal having an input clock signal period, (2) the third input signals include the first output signal and the second output signal, and (3) the third output includes an output clock signal having an output clock signal period, where the output clock signal period is a multiple of the input clock signal period.
摘要翻译：描述了时钟分频器。时钟分频器包括：正沿触发状态机，具有用于接收第一输入信号的第一输入端和用于提供第一输出信号的第一输出端; 负边缘触发状态机，具有用于接收第二输入信号的第二输入和用于提供第二输出信号的第二输出; 以及耦合到所述正沿触发状态机和所述负沿触发状态机的第一组合逻辑，所述第一组合逻辑具有用于接收第三输入信号的第三输入和用于提供第三输出信号的第三输出，其中（1）第一输入信号和第二输入信号中的至少一个包括具有输入时钟信号周期的输入时钟信号，（2）第三输入信号包括第一输出信号和第二输出信号，以及（3）第三输出包括具有输出时钟信号周期的输出时钟信号，其中输出时钟信号周期是输入时钟信号周期的倍数。

5. 发明授权

US08659334B2 Frequency control clock tuning circuitry 有权
标题翻译：频率控制时钟调谐电路
公开(公告)号：US08659334B2
公开(公告)日：2014-02-25
申请号：US13543724
申请日：2012-07-06
申请人： Teik Wah Lim , Eng Huat Lee , Ie Chen Chia , Thow Pang Chong , Boon Jin Ang , Kim Pin Tan
发明人： Teik Wah Lim , Eng Huat Lee , Ie Chen Chia , Thow Pang Chong , Boon Jin Ang , Kim Pin Tan
IPC分类号： H03L7/06
CPC分类号： H03L7/081 , G11C17/16 , G11C29/023 , G11C29/028 , G11C2029/4402 , H03L7/08
摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.
摘要翻译：公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。控制块读取存储在可编程保险丝中的设置或数据。耦合到控制块的调谐电路接收由控制块发送的延迟。调谐电路允许调节IC而不改变制造掩模。调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。

6. 发明授权

US08189362B2 Data encoding scheme to reduce sense current 有权
标题翻译：减少感应电流的数据编码方案
公开(公告)号：US08189362B2
公开(公告)日：2012-05-29
申请号：US13151230
申请日：2011-06-01
申请人： Jun Pin Tan , Tze Swan Tan , Chuan Khye Chai , Boon Jin Ang , Kar Keng Chua
发明人： Jun Pin Tan , Tze Swan Tan , Chuan Khye Chai , Boon Jin Ang , Kar Keng Chua
IPC分类号： G11C17/00
CPC分类号： G11C17/18 , G11C17/16
摘要： Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.
摘要翻译：公开了用于编码和解码熔丝数据以减少感测电流的技术。编码熔丝检测数据的实施例包括将熔丝数据的每一位反转并使用单独的熔丝作为标记位来记录数据反转。各个保险丝的状态可以表示不同的逻辑状态。熔断器可能会被烧断以指示逻辑电路，同样，未熔断的保险丝可能指示逻辑零。熔断的保险丝和未熔断的保险丝可能具有不同的电流消耗。与熔断保险丝相比，未熔断的保险丝可能消耗更多的感测电流。解码编码熔丝数据的另一个实施例包括嵌入式逻辑电路和单独的保险丝作为标志位。熔丝数据的编码和解码可以减少熔丝感应电流。

7. 发明授权

US07787314B2 Dynamic real-time delay characterization and configuration 有权
标题翻译：动态实时延迟表征和配置
公开(公告)号：US07787314B2
公开(公告)日：2010-08-31
申请号：US12208967
申请日：2008-09-11
申请人： Jun Pin Tan , Wei Yee Koay , Boon Jin Ang , Choong Kit Wong , Guang Sheng Soh
发明人： Jun Pin Tan , Wei Yee Koay , Boon Jin Ang , Choong Kit Wong , Guang Sheng Soh
IPC分类号： G11C7/10
CPC分类号： H03K19/1735 , G11C29/02 , G11C29/023 , G11C29/028 , H03K5/133
摘要： In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.
摘要翻译：在掩模可编程集成电路（例如结构化ASIC）中，延迟链提供由掩模可编程开关设置的延迟。延迟链接收输入以允许使用JTAG控制器覆盖延迟掩码编程的延迟。这允许测试不同的延迟。输入也可以由熔丝块提供，使得熔丝块可以覆盖掩模可编程开关，从而允许在掩模编程之后改变延迟。

8. 发明授权

US07565390B1 Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devices 有权
标题翻译：用于促进在可编程逻辑器件中进行乘法累加操作的电路的电路
公开(公告)号：US07565390B1
公开(公告)日：2009-07-21
申请号：US11089684
申请日：2005-03-23
申请人： Tat Mun Lui , Bee Yee Ng , Jun Pin Tan , Boon Jin Ang
发明人： Tat Mun Lui , Bee Yee Ng , Jun Pin Tan , Boon Jin Ang
IPC分类号： G06F7/48
CPC分类号： G06F7/5443 , G06F7/4991 , H03K19/17704 , H03K19/17732
摘要： In circuitry such as a programmable logic device (“PLD”), each of several multiplier blocks includes partial products generation circuitry and partial products addition circuitry. Two such multiplier blocks can be used together to provide multiply-accumulate (“MAC”) capability. The partial products addition circuitry in one of the paired blocks is used to add each successive product produced by the other paired block to a previous accumulation of products in the first-mentioned paired block. Provisions are also made for accumulating any overflow from operation of the partial products addition circuitry in the first-mentioned paired block.
摘要翻译：在诸如可编程逻辑器件（“PLD”）的电路中，几个乘法器块中的每一个包括部分乘积生成电路和部分乘积加法电路。两个这样的乘法器块可以一起使用以提供乘法累加（“MAC”）能力。一个配对块中的部分乘积加法电路用于将由另一个配对块产生的每个连续乘积加到先前提到的配对块中先前积累的乘积。还提供了在第一提到的配对块中累积部分产品添加电路的操作的任何溢出的规定。

9. 发明申请

US20080297192A1 TECHNIQUES FOR OPTIMIZING DESIGN OF A HARD INTELLECTUAL PROPERTY BLOCK FOR DATA TRANSMISSION 有权
标题翻译：优化硬件知识产权块数据传输设计的技术
公开(公告)号：US20080297192A1
公开(公告)日：2008-12-04
申请号：US12193532
申请日：2008-08-18
申请人： Darren van WAGENINGEN , Curt WORTMAN , Boon-Jin ANG , Thow-Pang CHONG , Dan MANSUR , Ali BURNEY
发明人： Darren van WAGENINGEN , Curt WORTMAN , Boon-Jin ANG , Thow-Pang CHONG , Dan MANSUR , Ali BURNEY
IPC分类号： H03K19/0175 , H03K19/177 , H01L25/00 , H04L12/46 , H04J3/06
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现为任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

10. 发明授权

US07218141B2 Techniques for implementing hardwired decoders in differential input circuits 有权
标题翻译：在差分输入电路中实现硬连线解码器的技术
公开(公告)号：US07218141B2
公开(公告)日：2007-05-15
申请号：US11007827
申请日：2004-12-07
申请人： Bee Yee Ng , Boon Jin Ang
发明人： Bee Yee Ng , Boon Jin Ang
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17744
摘要： Techniques are provided for improving signal timing characteristics of differential input/output (IO) circuits on programmable logic integrated circuits. A differential buffer receives differential signals applied to differential input pins. The output signals of the differential buffer are routed to two hard IO decoder blocks that are located in two adjacent rows/columns of programmable logic elements. Each IO decoder block has a data-in register that receives output signals of the differential buffer. The data-in registers in two adjacent IO decoder blocks support a double clocking technique. IO decoder blocks of the present invention have reduced setup times, hold times, and sampling windows relative to soft DDIO blocks, and have a minimal impact on die area.
摘要翻译：提供了用于改善可编程逻辑集成电路上的差分输入/输出（IO）电路的信号定时特性的技术。差分缓冲器接收施加到差分输入引脚的差分信号。差分缓冲器的输出信号被路由到位于可编程逻辑元件的两个相邻行/列中的两个硬IO解码器块。每个IO解码器块具有接收差分缓冲器的输出信号的数据输入寄存器。两个相邻IO解码器块中的数据输入寄存器支持双时钟技术。本发明的IO解码器块相对于软DDIO块具有减少的建立时间，保持时间和采样窗口，并且对芯片面积的影响最小。

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