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1. 发明授权

US09336066B2 Hybrid linear validation algorithm for software transactional memory (STM) systems 有权
标题翻译：用于软件事务存储器（STM）系统的混合线性验证算法
公开(公告)号：US09336066B2
公开(公告)日：2016-05-10
申请号：US12142097
申请日：2008-06-19
申请人： Adam Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Adam Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/52 , G06F9/46
CPC分类号： G06F9/526 , G06F9/466
摘要： A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation.
摘要翻译：这里描述了用于软件事务存储器（STM）的混合验证的方法和装置。在执行事务期间，当获取与数据元素相关联的元数据的所有权时，元数据被更新为对事务的所有权引用，以便能够进行有效的后续所有权测试。然而，在验证期间，对于某些条件，元数据从所有权引用更新为写入条目引用以实现高效验证。

2. 发明申请

US20150019825A1 SHARING VIRTUAL MEMORY-BASED MULTI-VERSION DATA BETWEEN THE HETEROGENEOUS PROCESSORS OF A COMPUTER PLATFORM 有权
标题翻译：在计算机平台的异构处理器之间共享基于虚拟内存的多版本数据
公开(公告)号：US20150019825A1
公开(公告)日：2015-01-15
申请号：US14503596
申请日：2014-10-01
申请人： Ying GAO , Hu CHEN , Shoumeng YAN , Xiaocheng ZHOU , Sai LUO , Bratin SAHA
发明人： Ying GAO , Hu CHEN , Shoumeng YAN , Xiaocheng ZHOU , Sai LUO , Bratin SAHA
IPC分类号： G06F12/10
CPC分类号： G06F12/109 , G06F9/466 , G06F9/544 , G06F15/167 , G06F2212/656 , G06F2212/657 , G06T1/20
摘要： A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit (GPU) and a shared virtual memory supported by a physical private memory space of at least one heterogeneous processor or a physical shared memory shared by the heterogeneous processor. The CPU (producer) may create shared multi-version data and store such shared multi-version data in the physical private memory space or the physical shared memory. The GPU (consumer) may acquire or access the shared multi-version data.
摘要翻译：计算机系统可以包括计算机平台和输入 - 输出设备。计算机平台可以包括多个异构处理器，包括中央处理单元（CPU）和图形处理单元（GPU）以及由至少一个异构处理器或物理共享存储器共享的物理专用存储器空间支持的共享虚拟存储器由异构处理器。 CPU（生产者）可以创建共享的多版本数据，并将这种共享的多版本数据存储在物理专用存储空间或物理共享存储器中。 GPU（消费者）可以获取或访问共享的多版本数据。

3. 发明授权

US08719807B2 Handling precompiled binaries in a hardware accelerated software transactional memory system 有权
标题翻译：在硬件加速软件事务内存系统中处理预编译的二进制文件
公开(公告)号：US08719807B2
公开(公告)日：2014-05-06
申请号：US11648008
申请日：2006-12-28
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
IPC分类号： G06F9/45 , G06F9/30 , G06F13/00
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/467 , G06F12/0837 , G06F2212/62
摘要： A method and apparatus for enabling a Software Transactional Memory (STM) with precompiled binaries is herein described. Upon encountering an access operation in a transaction, an annotation field associated with a memory location referenced by the access is checked. In response to the memory location representing a previous similar access within the transaction, the access is performed without access barriers. However, if the annotation field is in a default state representing no previous access during a pendancy of the transaction, then a mode of the processor is determined. If the processor mode is in implicit mode, an access handler/barrier is asynchronously executed. Conversely, in an explicit mode, a flag is set instead of asynchronously executing the handler. In addition, during compilation convert explicit and convert implicit instructions are inserted to intelligently convert modes for precompiled and newly compiled binaries. Furthermore, new versions of newly compiled functions may be inserted to provide strong atomicity between previously and newly compiled functions.
摘要翻译：这里描述了使用预编译二进制文件实现软件事务存储器（STM）的方法和装置。在事务中遇到访问操作时，检查与由访问引用的存储器位置相关联的注释字段。响应于表示事务内先前类似访问的存储器位置，访问被执行而没有访问障碍。然而，如果注释字段处于表示在事务的挂起期间没有先前访问的默认状态，则确定处理器的模式。如果处理器模式处于隐式模式，则异步执行访问处理程序/障碍。相反，在显式模式下，设置标志而不是异步执行处理程序。此外，在编译期间，转换显式和转换隐式指令将被智能地转换为预编译和新编译的二进制文件的模式。此外，可以插入新版本的新编译的函数，以便在先前和新编译的函数之间提供强大的原子性。

4. 发明授权

US08656113B2 Accelerating software lookups by using buffered or ephemeral stores 有权
标题翻译：通过使用缓冲或临时存储来加速软件查找
公开(公告)号：US08656113B2
公开(公告)日：2014-02-18
申请号：US13104681
申请日：2011-05-10
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Ethan Schuchman
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Ethan Schuchman
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F12/0811 , G06F2212/507
摘要： A method and apparatus for accelerating lookups in an address based table is herein described. When an address and value pair is added to an address based table, the value is privately stored in the address to allow for quick and efficient local access to the value. In response to the private store, a cache line holding the value is transitioned to a private state, to ensure the value is not made globally visible. Upon eviction of the privately held cache line, the information is not written-back to ensure locality of the value. In one embodiment, the address based table includes a transactional write buffer to hold addresses, which correspond to tentatively updated values during a transaction. Accesses to the tentative values during the transaction may be accelerated through use of annotation bits and private stores as discussed herein. Upon commit of the transaction, the values are copied to the location to make the updates globally visible.
摘要翻译：这里描述用于加速基于地址的表中的查找的方法和装置。当地址和值对被添加到基于地址的表中时，该值被私人地存储在地址中，以便能够快速高效地本地访问该值。响应于私有存储，保存该值的高速缓存行被转换到私有状态，以确保该值不是全局可见的。撤销私有高速缓存行时，信息不会被写回以确保价值的位置。在一个实施例中，基于地址的表包括用于保存地址的事务写入缓冲器，其对应于事务期间的暂时更新的值。可以通过使用如本文所讨论的注释位和专用存储来加速在事务期间访问临时值。在提交事务时，将将值复制到位置，以使更新全局可见。

5. 发明授权

US08555016B2 Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system 有权
公开(公告)号：US08555016B2
公开(公告)日：2013-10-08
申请号：US12337507
申请日：2008-12-17
申请人： Ali-Reza Adl-Tabatabai , Moshe Bach , Sion Berkowits , James Henry Cownie , Yang Ni , Jeffrey V. Olivier , Bratin Saha , Ady Tal , Adam Wele
发明人： Ali-Reza Adl-Tabatabai , Moshe Bach , Sion Berkowits , James Henry Cownie , Yang Ni , Jeffrey V. Olivier , Bratin Saha , Ady Tal , Adam Wele
IPC分类号： G06F12/00
CPC分类号： G06F9/467 , G06F9/528 , G06F17/30351 , G06F17/30353 , G06F17/30356 , G06F17/30359
摘要： A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.

6. 发明授权

US08521965B2 Hardware acceleration for a software transactional memory system 有权
标题翻译：软件交易内存系统的硬件加速
公开(公告)号：US08521965B2
公开(公告)日：2013-08-27
申请号：US12782518
申请日：2010-05-18
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
IPC分类号： G06F12/10
CPC分类号： G06F13/4243 , G06F9/3834 , G06F9/466 , G06F9/526
摘要： A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.
摘要翻译：一种用于加速事务执行的方法和装置。只有在事务中第一次访问共享内存条时，才会调用/执行与事务中的内存访问引用的共享内存条相关联的障碍。提供诸如事务字段/事务位之类的硬件支持来确定访问是否是在事务挂起期间对共享存储器行的第一次访问。另外，在积极的操作模式中，代表存储在共享存储器行中的元素的版本号的版本号在保存验证成本的承诺时不被存储和验证。而且，即使在谨慎的模式下，存储版本号以启用验证，如果在执行交易期间没有发生访问的共享内存条的驱逐，则可能不会产生验证成本。

7. 发明申请

US20130097607A1 METHOD, APPARATUS, AND SYSTEM FOR ADAPTIVE THREAD SCHEDULING IN TRANSACTIONAL MEMORY SYSTEMS 有权
标题翻译：方法，装置和系统用于自适应线程调度在交互式存储器系统中
公开(公告)号：US20130097607A1
公开(公告)日：2013-04-18
申请号：US13273695
申请日：2011-10-14
申请人： Brian T. Lewis , Bratin Saha
发明人： Brian T. Lewis , Bratin Saha
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/467 , G06F9/4881
摘要： An apparatus and method is described herein for adaptive thread scheduling in a transactional memory environment. A number of conflicts in a thread over time are tracked. And if the conflicts exceed a threshold, the thread may be delayed (adaptively scheduled) to avoid conflicts between competing threads. Moreover, a more complex version may track a number of transaction aborts within a first thread that are caused by a second thread over a period, as well as a total number of transactions executed by the first thread over the period. From the tracking, a conflict ratio is determined for the first thread with regard to the second thread. And when the first thread is to be scheduled, it may be delayed if the second thread is running and the conflict ratio is over a conflict ratio threshold.
摘要翻译：这里描述了一种在事务存储器环境中的自适应线程调度的装置和方法。跟踪线程中的一些冲突。如果冲突超过阈值，线程可能被延迟（自适应调度），以避免竞争线程之间的冲突。此外，更复杂的版本可以跟踪在一段时间内由第二线程引起的第一线程内的多个事务中止以及在该周期上由第一线程执行的事务的总数。从跟踪中，针对第二线程确定第一线程的冲突比。并且当第一个线程被调度时，如果第二个线程正在运行并且冲突比超过了冲突比阈值，它可能被延迟。

8. 发明申请

US20120297152A1 HARDWARE ACCELERATION OF A WRITE-BUFFERING SOFTWARE TRANSACTIONAL MEMORY 审中-公开
标题翻译：写硬缓存软件的硬件加速
公开(公告)号：US20120297152A1
公开(公告)日：2012-11-22
申请号：US13471841
申请日：2012-08-01
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3851 , G06F9/3863 , G06F9/467 , G06F12/0842
摘要： A method and apparatus for accelerating a software transactional memory (STM) system is described herein. Annotation field are associated with lines of a transactional memory. An annotation field associated with a line of the transaction memory is initialized to a first value upon starting a transaction. In response to encountering a read operation in the transaction, then annotation field is checked. If the annotation field includes a first value, the read is serviced from the line of the transaction memory without having to search an additional write space. A second and third value in the annotation field potentially indicates whether a read operation missed the transactional memory or a tentative value is stored in a write space. Additionally, an additional bit in the annotation field, may be utilized to indicate whether previous read operations have been logged, allowing for subsequent redundant read logging to be reduced.
摘要翻译：本文描述了用于加速软件事务存储器（STM）系统的方法和装置。注释字段与事务存储器的行相关联。与事务存储器的行相关联的注释字段在启动事务时被初始化为第一个值。响应于在事务中遇到读取操作，则检查注释字段。如果注释字段包含第一个值，则读取将从事务存储器的行提供服务，而不必搜索额外的写入空间。注释字段中的第二和第三个值潜在地指示读操作是否错过事务存储器或暂存值是否存储在写空间中。此外，注释字段中的另外一个位可以用于指示是否已经记录先前的读取操作，从而允许减少随后的冗余读取记录。

9. 发明申请

US20120179875A1 USING EPHEMERAL STORES FOR FINE-GRAINED CONFLICT DETECTION IN A HARDWARE ACCELERATED STM 有权
标题翻译：在硬件加速STM中使用EPHEMERAL STORES进行细粒度冲突检测
公开(公告)号：US20120179875A1
公开(公告)日：2012-07-12
申请号：US13346987
申请日：2012-01-10
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Quinn Jacobson
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Quinn Jacobson
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/14 , G06F8/458 , G06F9/52 , G06F9/522 , G06F12/0802 , G06F12/1483
摘要： A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have an arbitrary size, is associated with a filter word. The filter word is in a first default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access, such as a first read, from the data object, access barrier operations including an ephemeral/private store operation to set the filter word to a second state are performed. Upon a subsequent/redundant access, such as a second read, the access barrier operations are elided to accelerate the subsequent access, based on the filter word being set to the second state to indicate a previous access occurred.
摘要翻译：这里描述了用于硬件加速软件事务存储器系统中的细粒度过滤的方法和装置。可以具有任意大小的数据对象与过滤字相关联。当在事务的挂起期间没有发生来自数据对象的访问（例如读取）时，过滤器字处于第一默认状态。在从数据对象遇到诸如第一次读取的第一次访问时，执行包括将过滤词设置为第二状态的临时/私人存储操作的访问障碍操作。在诸如第二次读取的后续/冗余访问之后，基于滤波器字被设置为第二状态来指示先前访问发生，访问屏障操作被消除以加速后续访问。

10. 发明申请

US20120089760A1 Increasing Functionality Of A Reader-Writer Lock 有权
标题翻译：增加读写器锁的功能
公开(公告)号：US20120089760A1
公开(公告)日：2012-04-12
申请号：US13325688
申请日：2011-12-14
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00 , G06F12/14
CPC分类号： G06F12/145 , G06F9/4881 , G06F9/526
摘要： In one embodiment, the present invention includes a method for accessing a shared memory associated with a reader-writer lock according to a first concurrency mode, dynamically changing from the first concurrency mode to a second concurrency mode, and accessing the shared memory according to the second concurrency mode. In this way, concurrency modes can be adaptively changed based on system conditions. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于根据第一并发模式访问与读写器锁相关联的共享存储器的方法，该方法从第一并发模式动态地改变到第二并发模式，以及根据所述第一并发模式访问共享存储器第二并发模式。以这种方式，可以根据系统条件自适应地改变并发模式。描述和要求保护其他实施例。

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