专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09594565B2 Hardware acceleration of a write-buffering software transactional memory 有权
标题翻译：写缓冲软件事务内存的硬件加速
公开(公告)号：US09594565B2
公开(公告)日：2017-03-14
申请号：US13471841
申请日：2012-08-01
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
IPC分类号： G06F12/08 , G06F9/38 , G06F9/46
CPC分类号： G06F9/3834 , G06F9/3851 , G06F9/3863 , G06F9/467 , G06F12/0842
摘要： A method and apparatus for accelerating a software transactional memory (STM) system is described herein. Annotation field are associated with lines of a transactional memory. An annotation field associated with a line of the transaction memory is initialized to a first value upon starting a transaction. In response to encountering a read operation in the transaction, then annotation field is checked. If the annotation field includes a first value, the read is serviced from the line of the transaction memory without having to search an additional write space. A second and third value in the annotation field potentially indicates whether a read operation missed the transactional memory or a tentative value is stored in a write space. Additionally, an additional bit in the annotation field, may be utilized to indicate whether previous read operations have been logged, allowing for subsequent redundant read logging to be reduced.
摘要翻译：本文描述了用于加速软件事务存储器（STM）系统的方法和装置。注释字段与事务存储器的行相关联。与事务存储器的行相关联的注释字段在启动事务时被初始化为第一个值。响应于在事务中遇到读取操作，则检查注释字段。如果注释字段包含第一个值，则读取将从事务存储器的行提供服务，而不必搜索额外的写入空间。注释字段中的第二和第三个值潜在地指示读操作是否错过事务存储器或暂存值是否存储在写空间中。此外，注释字段中的另外一个位可以用于指示是否已经记录先前的读取操作，从而允许减少随后的冗余读取记录。

2. 发明授权

US08838908B2 Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STM 有权
标题翻译：在硬件加速STM中使用临时存储进行细粒度冲突检测
公开(公告)号：US08838908B2
公开(公告)日：2014-09-16
申请号：US13346987
申请日：2012-01-10
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Quinn Jacobson
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Quinn Jacobson
IPC分类号： G06F12/00 , G06F12/14 , G06F12/08
CPC分类号： G06F12/14 , G06F8/458 , G06F9/52 , G06F9/522 , G06F12/0802 , G06F12/1483
摘要： A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have an arbitrary size, is associated with a filter word. The filter word is in a first default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access, such as a first read, from the data object, access barrier operations including an ephemeral/private store operation to set the filter word to a second state are performed. Upon a subsequent/redundant access, such as a second read, the access barrier operations are elided to accelerate the subsequent access, based on the filter word being set to the second state to indicate a previous access occurred.
摘要翻译：这里描述了用于硬件加速软件事务存储器系统中的细粒度过滤的方法和装置。可以具有任意大小的数据对象与过滤字相关联。当在事务的挂起期间没有发生来自数据对象的访问（例如读取）时，过滤器字处于第一默认状态。在从数据对象遇到诸如第一次读取的第一次访问时，执行包括将过滤词设置为第二状态的临时/私人存储操作的访问障碍操作。在诸如第二次读取的后续/冗余访问之后，基于滤波器字被设置为第二状态来指示先前访问发生，访问屏障操作被消除以加速后续访问。

3. 发明授权

US08368892B2 Infrared spectroscopy 有权
标题翻译：红外光谱
公开(公告)号：US08368892B2
公开(公告)日：2013-02-05
申请号：US12695463
申请日：2010-01-28
申请人： Kenneth Tracton , Quinn Jacobson
发明人： Kenneth Tracton , Quinn Jacobson
IPC分类号： G01N21/00
CPC分类号： G01J3/42 , G01J3/02 , G01J3/021 , G01J3/0291 , G01J3/14 , G01N21/3504
摘要： An apparatus includes an optical source providing an optical beam; a splitter configured to split the optical beam into a sample beam and a reference beam; a sample path containing a sample material to be analyzed, the sample beam being directed through the sample path so as to interact with the sample material; a reference path containing a reference material, the reference beam being directed through the reference path so as to interact with the reference material; a disperser configured to receive the sample beam after it exits the sample path and to receive the reference beam after it exits the reference path, the disperser outputting a dispersed sample beam and a dispersed reference beam; and a photodetector disposed to receive the dispersed sample beam and the dispersed reference beam and outputting electrical signals comprised of data indicative of a spectra of the sample beam after it exits the sample path and a spectra of the reference beam after it exits the reference path. In one embodiment the apparatus further includes a data processor connected with a memory storing a software program configured to process the data to detect a presence of at least one type of molecular species that includes the sample material; and a transmitter configured to transmit the processed data to a receiver. In another embodiment the apparatus includes a transmitter configured to transmit the data to a remote receiver for processing.
摘要翻译：一种装置包括提供光束的光源; 分配器，被配置为将光束分成样品光束和参考光束; 包含待分析的样品材料的样品路径，所述样品光束被引导通过所述样品路径以便与所述样品材料相互作用; 包含参考材料的参考路径，所述参考光束通过所述参考路径被引导以与所述参考物质相互作用; 分散器，被配置为在离开所述采样路径之后接收所述采样光束，并且在所述参考光束离开所述参考路径之后接收所述参考光束，所述分散器输出分散的采样光束和分散的参考光束; 以及光电检测器，被设置为接收分散的样本光束和分散的参考光束，并且输出由表示样品光束离开采样路径之后的光谱的数据组成的电信号，以及参考光束离开参考路径后的光谱。在一个实施例中，该装置还包括与存储器相连的数据处理器，该存储器存储软件程序，该软件程序被配置为处理该数据以检测至少一种类型的包括样品材料的分子物种的存在; 以及被配置为将处理的数据发送到接收机的发射机。在另一个实施例中，该装置包括被配置为将数据发送到远程接收机进行处理的发射机。

4. 发明申请

US20090143966A1 METHODS, APPARATUSES, AND COMPUTER PROGRAM PRODUCT FOR TRAFFIC DATA AGGREGATION USING VIRTUAL TRIP LINES AND GPS-ENABLED MOBILE HANDSETS 有权
标题翻译：方法，装置和计算机程序产品，用于使用虚拟行车线和GPS启动手机的交通数据聚合
公开(公告)号：US20090143966A1
公开(公告)日：2009-06-04
申请号：US11948779
申请日：2007-11-30
申请人： Quinn Jacobson , Baik Hoh , Murali Annavaram
发明人： Quinn Jacobson , Baik Hoh , Murali Annavaram
IPC分类号： G08G1/01 , G08G1/052
CPC分类号： G08G1/0104 , G08G1/052
摘要： A device for determining when a virtual trip line has been crossed or traversed is provided. The device includes a memory for storing the virtual trip lines which are defined pairs of location descriptors corresponding to a geographic area. The device further includes a processor that is capable of determining the location of the device when it crosses a virtual trip line as well as its speed and direction. The processing element is further capable of sending this information to another electronic device such as a server that may determine a number of vehicles crossing a virtual trip line for a specified amount of time, the average speed of vehicles crossing the virtual trip line and the traffic density in a region near the virtual trip line. The device is capable of receiving the information that was determined by the server.
摘要翻译：提供了一种用于确定虚拟跳闸线何时已被越过或穿过的装置。该设备包括用于存储虚拟跳闸线的存储器，虚拟跳闸线是对应于地理区域的定义的位置描述符对。该设备还包括处理器，其能够在穿过虚拟跳闸线以及其速度和方向时确定设备的位置。处理元件还能够将该信息发送到诸如可以确定跨越虚拟跳闸线路的车辆数量达指定时间量的其他电子设备，穿过虚拟跳闸线路的车辆的平均速度和交通在虚拟跳闸线附近的区域的密度。该设备能够接收由服务器确定的信息。

5. 发明申请

US20080299943A1 APPARATUSES, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR DETERMINING A CHARGE FOR INFORMATIONAL MATERIAL 审中-公开
标题翻译：用于确定信息资料收费的装置，方法和计算机程序产品
公开(公告)号：US20080299943A1
公开(公告)日：2008-12-04
申请号：US11757602
申请日：2007-06-04
申请人： Quinn Jacobson , Govind Krishnamurthi
发明人： Quinn Jacobson , Govind Krishnamurthi
IPC分类号： H04M11/00
CPC分类号： G01S5/0009 , G01S5/02 , G06Q20/123 , G06Q20/14 , G06Q20/32 , G06Q20/3224
摘要： Provided is an apparatus for determining a charge to an entity associated with informational material disseminated to at least one mobile terminal. The apparatus includes a processing unit that may be configured to obtain respective location data of the mobile terminal during and subsequent to rendering of the informational material at the mobile terminal. A billing unit may be configured to determine a charge to an entity associated with the informational material based at least in part on movement of the at least one mobile terminal subsequent to rendering of the informational material as indicated by the location data. Corresponding methods and computer program products are also provided.
摘要翻译：提供了一种用于确定向与至少一个移动终端传播的信息资料相关联的实体的费用的装置。该装置包括处理单元，其可被配置为在移动终端呈现信息资料期间和之后获得移动终端的相应位置数据。计费单元可以被配置为至少部分地基于由位置数据指示的呈现信息材料之后的至少一个移动终端的移动来确定与信息资料相关联的实体的费用。还提供了相应的方法和计算机程序产品。

6. 发明申请

US20060294326A1 Primitives to enhance thread-level speculation 有权
标题翻译：提高线程级推测的原语
公开(公告)号：US20060294326A1
公开(公告)日：2006-12-28
申请号：US11165639
申请日：2005-06-23
申请人： Quinn Jacobson , Hong Wang , John Shen , Gautham Chinya , Per Hammarlund , Xiang Zou , Bryant Bigbee , Shivnandan Kaushik
发明人： Quinn Jacobson , Hong Wang , John Shen , Gautham Chinya , Per Hammarlund , Xiang Zou , Bryant Bigbee , Shivnandan Kaushik
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F9/30087 , G06F9/30101 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.
摘要翻译：处理器可以包括地址监视表和原子更新表以支持推测性线程。处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或指令清除与陷阱/异常/中断处理相关联的状态位之一。还描述和要求保护其他实施例。

7. 发明申请

US20060064567A1 Translating loads for accelerating virtualized partition 有权
标题翻译：翻译用于加速虚拟化分区的加载
公开(公告)号：US20060064567A1
公开(公告)日：2006-03-23
申请号：US11135838
申请日：2005-05-23
申请人： Quinn Jacobson , Shailender Chaudhry
发明人： Quinn Jacobson , Shailender Chaudhry
IPC分类号： G06F12/08
CPC分类号： G06F12/1054 , G06F9/45558 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F2009/45583 , G06F2212/151
摘要： A system, which includes a processor that includes a plurality of cores, generates an address translation when there is a miss in a translation lookaside buffer (TLB). A hypervisor utilizes a translating load instruction that upon execution on the processor generates a data portion of a TLB entry. Execution of the translating load instruction utilizes information from a real-to-physical address translation table entry and information provided in the call to the translating load instruction to synthesize the data portion of a new virtual-to-physical translation table entry.
摘要翻译：包括多个核的处理器的系统在翻译后备缓冲器（TLB）中存在遗漏时产生地址转换。管理程序使用翻译加载指令，其在处理器上执行时生成TLB条目的数据部分。翻译加载指令的执行利用来自实际到物理地址转换表项的信息和在转换加载指令的调用中提供的信息以合成新的虚拟 - 物理转换表条目的数据部分。

8. 发明申请

US20050223385A1 Method and structure for explicit software control of execution of a thread including a helper subthread 审中-公开
标题翻译：用于显式软件控制执行包括辅助子线程的线程的方法和结构
公开(公告)号：US20050223385A1
公开(公告)日：2005-10-06
申请号：US11083163
申请日：2005-03-16
申请人： Christof Braun , Quinn Jacobson , Shailender Chaudhry , Marc Tremblay
发明人： Christof Braun , Quinn Jacobson , Shailender Chaudhry , Marc Tremblay
IPC分类号： G06F15/76
CPC分类号： G06F9/3851 , G06F9/3005 , G06F9/3802 , G06F9/383 , G06F9/3863 , G06F9/462
摘要： Software instructions in a single thread code sequence with a helper subthread are executed on a processor of a computer system. The execution causes the computer system, for example, to (i) determine whether information associated with a long latency instruction is available, and when the data is unavailable, to (ii) snapshot a state of the computer system and maintain a capability to roll back to that snapshot state, (iii) execute the helper instruction in the helper subthread, and (iv) roll back to the snapshot state upon completion of execution of the helper instructions in the helper subthread and continue execution. The helper subthread, for example prefetches data while waiting for the long latency instruction to complete.
摘要翻译：具有辅助子线程的单线程代码序列中的软件指令在计算机系统的处理器上执行。执行导致计算机系统，例如，（i）确定与长延迟指令相关联的信息是否可用，以及当数据不可用时，（ii）快照计算机系统的状态并保持滚动的能力返回到该快照状态，（iii）执行助手子线程中的帮助器指令，以及（iv）在完成辅助程序副线程中的帮助器指令的执行后，回滚到快照状态，并继续执行。辅助子线程，例如在等待长延迟指令完成时预取数据。

9. 发明授权

US08719807B2 Handling precompiled binaries in a hardware accelerated software transactional memory system 有权
标题翻译：在硬件加速软件事务内存系统中处理预编译的二进制文件
公开(公告)号：US08719807B2
公开(公告)日：2014-05-06
申请号：US11648008
申请日：2006-12-28
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
IPC分类号： G06F9/45 , G06F9/30 , G06F13/00
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/467 , G06F12/0837 , G06F2212/62
摘要： A method and apparatus for enabling a Software Transactional Memory (STM) with precompiled binaries is herein described. Upon encountering an access operation in a transaction, an annotation field associated with a memory location referenced by the access is checked. In response to the memory location representing a previous similar access within the transaction, the access is performed without access barriers. However, if the annotation field is in a default state representing no previous access during a pendancy of the transaction, then a mode of the processor is determined. If the processor mode is in implicit mode, an access handler/barrier is asynchronously executed. Conversely, in an explicit mode, a flag is set instead of asynchronously executing the handler. In addition, during compilation convert explicit and convert implicit instructions are inserted to intelligently convert modes for precompiled and newly compiled binaries. Furthermore, new versions of newly compiled functions may be inserted to provide strong atomicity between previously and newly compiled functions.
摘要翻译：这里描述了使用预编译二进制文件实现软件事务存储器（STM）的方法和装置。在事务中遇到访问操作时，检查与由访问引用的存储器位置相关联的注释字段。响应于表示事务内先前类似访问的存储器位置，访问被执行而没有访问障碍。然而，如果注释字段处于表示在事务的挂起期间没有先前访问的默认状态，则确定处理器的模式。如果处理器模式处于隐式模式，则异步执行访问处理程序/障碍。相反，在显式模式下，设置标志而不是异步执行处理程序。此外，在编译期间，转换显式和转换隐式指令将被智能地转换为预编译和新编译的二进制文件的模式。此外，可以插入新版本的新编译的函数，以便在先前和新编译的函数之间提供强大的原子性。

10. 发明授权

US08521965B2 Hardware acceleration for a software transactional memory system 有权
标题翻译：软件交易内存系统的硬件加速
公开(公告)号：US08521965B2
公开(公告)日：2013-08-27
申请号：US12782518
申请日：2010-05-18
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
IPC分类号： G06F12/10
CPC分类号： G06F13/4243 , G06F9/3834 , G06F9/466 , G06F9/526
摘要： A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.
摘要翻译：一种用于加速事务执行的方法和装置。只有在事务中第一次访问共享内存条时，才会调用/执行与事务中的内存访问引用的共享内存条相关联的障碍。提供诸如事务字段/事务位之类的硬件支持来确定访问是否是在事务挂起期间对共享存储器行的第一次访问。另外，在积极的操作模式中，代表存储在共享存储器行中的元素的版本号的版本号在保存验证成本的承诺时不被存储和验证。而且，即使在谨慎的模式下，存储版本号以启用验证，如果在执行交易期间没有发生访问的共享内存条的驱逐，则可能不会产生验证成本。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式