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1. 发明申请

US20110034069A1 Electronic Guitar Harness Component Connector 有权
标题翻译：电子吉他线束组件连接器
公开(公告)号：US20110034069A1
公开(公告)日：2011-02-10
申请号：US12854166
申请日：2010-08-10
申请人： Bruce Ledley Jacob
发明人： Bruce Ledley Jacob
IPC分类号： H01R12/24 , H01R3/00
CPC分类号： G10H1/32 , H01R12/79
摘要： An electronic guitar harness component connector uses ribbon cables and circuit boards to interconnect electronic components in an electric guitar harness. The use of ribbon cables and circuit boards to interconnect electronic components in the harness solves the problem of hand-soldered joints of discrete wires. It eliminates the need for the hand-soldered joints of discrete wires, and multiple wires. Discrete wires are replaced with a single ribbon cable and/or circuit boards to interconnect electronic components.
摘要翻译：电子吉他线束组件连接器使用带状电缆和电路板来互连电吉他线束中的电子部件。使用带状电缆和电路板将线束中的电子部件互连解决了离散电线的手焊接头的问题。它消除了对分立导线和多根导线的手焊接头的需要。分离电线被单个带状电缆和/或电路板替代以互连电子部件。

2. 发明申请

US20160335092A1 Using Very Long Instruction Word VLIW Cores In Many-Core Architectures 审中-公开
标题翻译：在多核架构中使用超长指令字VLIW内核
公开(公告)号：US20160335092A1
公开(公告)日：2016-11-17
申请号：US15046438
申请日：2016-02-17
申请人： Bruce Ledley Jacob
发明人： Bruce Ledley Jacob
IPC分类号： G06F9/38 , G06F15/76
CPC分类号： G06F15/76 , G06F1/32 , G06F8/45 , G06F9/30138 , G06F9/30141 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30185 , G06F9/3826 , G06F9/384 , G06F9/3861
摘要： Current ultra-high-performance computers execute instructions at the rate of roughly 10 PFLOPS and dissipate power in the range of 10 MW. The next generation of exascale machines will need to execute instructions at EFLOPS rates-100× as fast as today's—but without dissipating any more power. To achieve this challenging goal, the emphasis will be on power-efficient execution, and for this we propose VLIW-CMP as a general architectural approach that will improve significantly on the power efficiency of existing solutions. To make VLIW work efficiently, we describe multiple mechanisms: software register-renaming, a hardware facility in which data forwarding is controlled completely by the compiler; and a disjunct register file, which reduces both the die area required by the register file and the power dissipated by the register file. The preferred embodiments disclose power saving methods and devices for use in computers with parallel processing units, or any high-performance processors with multiple pipelines or parallel processing. These power saving methods and devices include especially especially (1) data forwarding and register-file ports, (2) the use of VLIW core architectures to reduce a manycore chip's off-chip memory-bandwidth needs, (3) renaming registers in software, and (4) disjunct register files, which are widely applicable to any processor with multiple pipelines.
摘要翻译：当前的超高性能计算机以大约10 PFLOPS的速率执行指令，耗散功率在10兆瓦。下一代Exascale机器将需要执行EFLOPS速率的指令，如今天的100倍，但不会消耗更多的功率。为了实现这一具有挑战性的目标，重点将放在功率高效的执行上，为此，我们提出VLIW-CMP作为通用架构方法，可以显着改善现有解决方案的功率效率。为了使VLIW有效地工作，我们描述了多种机制：软件注册重命名，其中数据转发由编译器完全控制的硬件设施; 和一个分离的寄存器文件，可以减少寄存器文件所需的管芯面积和寄存器文件消耗的功耗。优选实施例公开了用于具有并行处理单元的计算机或具有多个管线或并行处理的任何高性能处理器的功率节省方法和设备。这些省电方法和设备尤其尤其包括（1）数据转发和注册文件端口，（2）使用VLIW核心架构来减少芯片内存的带宽需求，（3）重新命名软件中的寄存器，和（4）分离寄存器文件，其广泛适用于具有多个管线的任何处理器。

3. 发明申请

US20160285741A1 Efficient High-Radix Networks for Large Scale Computer Systems 审中-公开
标题翻译：用于大型计算机系统的高效高基数网络
公开(公告)号：US20160285741A1
公开(公告)日：2016-09-29
申请号：US15130957
申请日：2016-04-16
申请人： Bruce Ledley Jacob
发明人： Bruce Ledley Jacob
IPC分类号： H04L12/715 , H04L12/707 , H04L12/727 , H04L12/755 , H04L12/703
CPC分类号： H04L45/04 , H04L45/021 , H04L45/121 , H04L45/22 , H04L45/28
摘要： An interconnection method is disclosed for connecting multiple sub-neworks providing significant improvements in performance and reductions in cost. The method interconnects copies of a given sub-network, e.g., a 2-hop Moore graph sub-network, or a 2-hop Flattened Butterfly sub-network. Each sub-network connects to every other sub-network over multiple links, and the originating nodes in each sub-network lie at a maximum distance of 1 hop from all other nodes in that sub-network. This set of originating nodes connects to a set of similarly chosen nodes in another sub-network, for each pair of sub-networks, to produce a system-wide diameter of 4 (maximum of 4 hops between any two nodes), given 2-hop sub-networks. For example, to reach a given remote sub-network j, starting at a node in sub-network i, a packet must first reach any one of the local sub-network i's originating nodes, connected to nodes in remote sub-network j. This takes at most one hop. Another hop reaches the remote sub-network j, where it takes at most two hops to reach the desired node. The disclosed interconnection methodology scales up to billions of nodes in an efficient manner, keeping the number of required ports per router low, the number of hops to connect any given pair of nodes low, the bisection bandwidths high, and it provides easily determined routing. Moreover, because each sub-network can be identical, only one PCB design for the subnet needs to be designed, tested, and manufactured. All of these design features significantly reduce costs and while also significantly increasing performance.
摘要翻译：公开了一种互连方法，用于连接多个子网，提供显着的性能改进和成本降低。该方法将给定子网络的副本互连，例如2跳摩尔图子网络或2跳平展蝴蝶子网络。每个子网络通过多个链路连接到每个其他子网络，并且每个子网络中的始发节点处于与该子网络中的所有其他节点的1跳的最大距离。这组起始节点连接到另一个子网络中对于每对子网络的一组类似选择的节点，以产生系统范围直径为4（任何两个节点之间最多4跳），给定2- 跳子网。例如，为了到达给定的远程子网j，从子网i中的一个节点开始，分组必须首先到达本地子网i的始发节点中的任何一个，连接到远程子网j中的节点。这最多需要一跳。另一跳到达远程子网j，其中最多需要两个跳到达所需的节点。所公开的互连方法以有效的方式扩展到数十亿个节点，保持每个路由器所需端口的数量较少，连接任何给定的节点对的跳数，二分带宽高，并且它提供容易确定的路由。此外，由于每个子网可以相同，所以只需要设计，测试和制造一个子网的PCB设计。所有这些设计功能显着降低了成本，同时也显着提高了性能。

4. 发明申请

US20100208916A1 Volume-Adjustment Circuit for Equilibrating Pickup Settings 有权
标题翻译：用于平衡拾取设置的音量调节电路
公开(公告)号：US20100208916A1
公开(公告)日：2010-08-19
申请号：US12371224
申请日：2009-02-13
申请人： Bruce Ledley Jacob
发明人： Bruce Ledley Jacob
IPC分类号： H03G3/00
CPC分类号： G10H3/186 , G10H1/18
摘要： The disclosed volume-adjustment circuit sets the volume of each pickup setting in a topology-setting switch independent of other pickup topology settings in the switch. The volume-adjustment circuit has three parts: (1) a pickup topology selection switch that selects separate pickup-topologies, (2) separate and independent signal paths for chosen pickup-topologies, and (3) separate volume adjustment circuits in electrically separate and independent signal paths. Thus, the disclosure provides separate volume adjustment for selected pickup topologies of the pickup topology selection switch.
摘要翻译：所公开的音量调节电路将拓扑设置开关中的每个拾音器设置的音量设置为与开关中的其它拾音器拓扑设置无关。音量调节电路有三个部分：（1）一个拾音器拓扑选择开关，选择独立的拾音器，（2）独立和独立的信号路径，用于选择的拾音器，以及（3）分开的音量调节电路，独立的信号路径。因此，本公开为拾取器拓扑选择开关的选择的拾取拓扑提供单独的音量调节。

5. 发明申请

US20090308233A1 PROGRAMABLE SWITCH FOR CONFIGURING CIRCUIT TOPOLOGIES 有权
标题翻译：用于配置电路拓扑的可编程开关
公开(公告)号：US20090308233A1
公开(公告)日：2009-12-17
申请号：US12234682
申请日：2008-09-21
申请人： Bruce Ledley Jacob
发明人： Bruce Ledley Jacob
IPC分类号： G10H3/18
CPC分类号： G10H1/18 , G10H3/186 , G10H2220/291
摘要： The disclosed invention is a programmable switch for configuring circuit topologies. The switch can be any type of mechanical or electronic switch. Every setting of the switch can be programmed by a user, selecting topologies such as circuit elements in series, in parallel, in phase or out of phase. In a dual switch embodiment, the first switch selects the circuit elements to be used, and the second switch configures those selected elements in a wide variety of topologies. This division in switch circuit design between element selection and then topology provides an extremely wide range of circuit topologies available, unlike prior art designs.
摘要翻译：所公开的发明是用于配置电路拓扑的可编程开关。开关可以是任何类型的机械或电子开关。交换机的每个设置都可以由用户进行编程，并行地进行串并联选择拓扑，例如电路元件，同相或异相。在双开关实施例中，第一开关选择要使用的电路元件，并且第二开关将这些选择的元件配置在各种拓扑中。元件选择和拓扑之间的开关电路设计中的这种划分提供了与现有技术设计不同的可用电路拓扑结构的极宽范围。

6. 发明申请

US20170195211A9 Efficient High-Radix Networks for Large Scale Computer Systems 审中-公开
公开(公告)号：US20170195211A9
公开(公告)日：2017-07-06
申请号：US15130957
申请日：2016-04-16
申请人： Bruce Ledley Jacob
发明人： Bruce Ledley Jacob
IPC分类号： H04L12/715 , H04L12/707 , H04L12/727 , H04L12/755 , H04L12/703
CPC分类号： H04L45/04 , H04L45/021 , H04L45/121 , H04L45/22 , H04L45/28
摘要： An interconnection method is disclosed for connecting multiple sub-neworks providing significant improvements in performance and reductions in cost. The method interconnects copies of a given sub-network, e.g., a 2-hop Moore graph sub-network, or a 2-hop Flattened Butterfly sub-network. Each sub-network connects to every other sub-network over multiple links, and the originating nodes in each sub-network lie at a maximum distance of 1 hop from all other nodes in that sub-network. This set of originating nodes connects to a set of similarly chosen nodes in another sub-network, for each pair of sub-networks, to produce a system-wide diameter of 4 (maximum of 4 hops between any two nodes), given 2-hop sub-networks. For example, to reach a given remote sub-network j, starting at a node in sub-network i, a packet must first reach any one of the local sub-network i's originating nodes, connected to nodes in remote sub-network j. This takes at most one hop. Another hop reaches the remote sub-network j, where it takes at most two hops to reach the desired node. The disclosed interconnection methodology scales up to billions of nodes in an efficient manner, keeping the number of required ports per router low, the number of hops to connect any given pair of nodes low, the bisection bandwidths high, and it provides easily determined routing. Moreover, because each sub-network can be identical, only one PCB design for the subnet needs to be designed, tested, and manufactured. All of these design features significantly reduce costs and while also significantly increasing performance.

7. 发明申请

US20160253123A1 NVMM: An Extremely Large, Logically Unified, Sequentially Consistent Main-Memory System 审中-公开
标题翻译： NVMM：一个非常大的，逻辑统一的，顺序一致的主内存系统
公开(公告)号：US20160253123A1
公开(公告)日：2016-09-01
申请号：US14662236
申请日：2015-03-18
申请人： Bruce Ledley Jacob
发明人： Bruce Ledley Jacob
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F12/0806 , G06F9/4401 , G06F11/00 , G06F12/0246 , G06F12/0873 , G06F12/1009 , G06F13/16 , G06F13/1694 , G06F2212/1016 , G06F2212/1032 , G06F2212/202 , G06F2212/282 , G06F2212/313 , G06F2212/7201 , G06F2212/7208 , G11C29/82
摘要： Embodiments of both a non-volatile main memory (NVMM) single node and a multi-node computing system are disclosed. One embodiment of the NVMM single node system has a cache subsystem composed of all DRAM, a large main memory subsystem of all NAND flash, and provides different address-mapping policies for each software application. The NVMM memory controller provides high, sustained bandwidths for client processor requests, by managing the DRAM cache as a large, highly banked system with multiple ranks and multiple DRAM channels, and large cache blocks to accommodate large NAND flash pages. Multi-node systems organize the NVMM single nodes in a large inter-connected cache/flash main memory low-latency network. The entire interconnected flash system exports a single address space to the client processors and, like a unified cache, the flash system is shared in a way that can be divided unevenly among its client processors: client processors that need more memory resources receive it at the expense of processors that need less storage. Multi-node systems have numerous configurations, from board-area networks, to multi-board networks, and all nodes are connected in various Moore graph topologies. Overall, the disclosed memory architecture dissipates less power per GB than traditional DRAM architectures, uses an extremely large solid-state capacity of a terabyte or more of main memory per CPU socket, with a cost-per-bit approaching that of NAND flash memory, and performance approaching that of an all DRAM system.
摘要翻译：公开了非易失性主存储器（NVMM）单节点和多节点计算系统的实施例。 NVMM单节点系统的一个实施例具有由所有DRAM，所有NAND闪存的大型主存储器子系统组成的高速缓存子系统，并为每个软件应用提供不同的地址映射策略。 NVMM存储器控制器通过将DRAM缓存管理为具有多个级别和多个DRAM通道的大型，高度存储的系统以及大型缓存块来容纳大型NAND闪存页面，为客户端处理器请求提供高持续带宽。多节点系统在大型互连缓存/闪存主内存低延迟网络中组织NVMM单个节点。整个互连的闪存系统将单个地址空间导出到客户端处理器，并且像统一的缓存一样，闪存系统以其客户端处理器之间不均匀分配的方式进行共享：需要更多内存资源的客户端处理器在需要更少存储的处理器的费用。多节点系统具有从板区域网络到多板网络的众多配置，并且所有节点都以各种Moore图形拓扑连接。总体而言，所公开的存储器架构消耗的功率比传统DRAM架构要少，每个CPU插槽使用一个TB级或更多主存储器的极大固态容量，NAND闪存的每位成本接近，和性能接近全DRAM系统。

8. 外观设计

USD622305S1 Musical instrument fingerboard inlay 有权
标题翻译：乐器指板镶嵌
公开(公告)号：USD622305S1
公开(公告)日：2010-08-24
申请号：US29333476
申请日：2009-03-10
申请人： Bruce Ledley Jacob
设计人： Bruce Ledley Jacob

9. 发明授权

US08445770B2 Programable switch for configuring circuit topologies 有权
标题翻译：用于配置电路拓扑的可编程开关
公开(公告)号：US08445770B2
公开(公告)日：2013-05-21
申请号：US12234682
申请日：2008-09-21
申请人： Bruce Ledley Jacob
发明人： Bruce Ledley Jacob
IPC分类号： G10H3/12 , G10H1/02 , H03K19/173
CPC分类号： G10H1/18 , G10H3/186 , G10H2220/291
摘要： The disclosed invention is a programmable switch for configuring circuit topologies. The switch can be any type of mechanical or electronic switch. Every setting of the switch can be programmed by a user, selecting topologies such as circuit elements in series, in parallel, in phase or out of phase. In a dual switch embodiment, the first switch selects the circuit elements to be used, and the second switch configures those selected elements in a wide variety of topologies. This division in switch circuit design between element selection and then topology provides an extremely wide range of circuit topologies available, unlike prior art designs.
摘要翻译：所公开的发明是用于配置电路拓扑的可编程开关。开关可以是任何类型的机械或电子开关。交换机的每个设置都可以由用户进行编程，并行地进行串并联选择拓扑，例如电路元件，同相或异相。在双开关实施例中，第一开关选择要使用的电路元件，并且第二开关将这些选择的元件配置在各种拓扑中。元件选择和拓扑之间的开关电路设计中的这种划分提供了与现有技术设计不同的可用电路拓扑结构的极宽范围。

10. 发明授权

US08324495B2 Volume-adjustment circuit for equilibrating pickup settings 有权
标题翻译：用于平衡拾音器设置的音量调节电路
公开(公告)号：US08324495B2
公开(公告)日：2012-12-04
申请号：US12371224
申请日：2009-02-13
申请人： Bruce Ledley Jacob
发明人： Bruce Ledley Jacob
IPC分类号： G10H1/46 , G10H3/12
CPC分类号： G10H3/186 , G10H1/18
摘要： The disclosed volume-adjustment circuit sets the volume of each pickup setting in a topology-setting switch independent of other pickup topology settings in the switch. The volume-adjustment circuit has three parts: (1) a pickup topology selection switch that selects separate pickup-topologies, (2) separate and independent signal paths for chosen pickup-topologies, and (3) separate volume adjustment circuits in electrically separate and independent signal paths. Thus, the disclosure provides separate volume adjustment for selected pickup topologies of the pickup topology selection switch.
摘要翻译：所公开的音量调节电路将拓扑设置开关中的每个拾音器设置的音量设置为与开关中的其它拾音器拓扑设置无关。音量调节电路有三个部分：（1）一个拾音器拓扑选择开关，选择独立的拾音器，（2）独立和独立的信号路径，用于选择的拾音器，以及（3）分开的音量调节电路，独立的信号路径。因此，本公开为拾取器拓扑选择开关的选择的拾取拓扑提供单独的音量调节。

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