专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08060669B2 Memory controller with automatic command processing unit and memory system including the same 有权
标题翻译：具有自动命令处理单元和内存系统的内存控制器包括相同的
公开(公告)号：US08060669B2
公开(公告)日：2011-11-15
申请号：US11692482
申请日：2007-03-28
申请人： Bum-Seok Yu
发明人： Bum-Seok Yu
IPC分类号： G06F3/00 , G06F5/00 , G06F12/00 , G06F13/00 , G06F13/28 , G11C7/10
CPC分类号： G06F12/1009 , G06F13/1673 , G06F2212/2022
摘要： Provided is a memory controller configured to control a flash memory device. The memory controller includes: a buffer memory configured to store data to be written in the flash memory device; a buffer memory interface configured to control read and write operations of the buffer memory; and an automatic command processing unit configured to interpret a data command generated by a host hardware device.
摘要翻译：提供了一种被配置为控制闪存设备的存储器控制器。存储器控制器包括：缓冲存储器，被配置为存储要写入闪存器件的数据; 缓冲存储器接口，被配置为控制缓冲存储器的读和写操作; 以及自动命令处理单元，被配置为解释由主机硬件设备生成的数据命令。

2. 发明申请

US20100241930A1 ERROR CORRECTING DEVICE, METHOD OF ERROR CORRECTION THEREOF, AND MEMORY DEVICE AND DATA PROCESSING SYSTEM INCLUDING OF THE SAME 有权
标题翻译：错误校正装置，其错误校正方法和存储器件以及包括其的数据处理系统
公开(公告)号：US20100241930A1
公开(公告)日：2010-09-23
申请号：US12720903
申请日：2010-03-10
申请人： Sil Wan CHANG , Bum Seok Yu , Sang Kyoo Jeong , Dong Gi Lee
发明人： Sil Wan CHANG , Bum Seok Yu , Sang Kyoo Jeong , Dong Gi Lee
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2927 , G06F11/1012 , H03M13/09 , H03M13/13 , H03M13/2906 , H03M13/37 , H03M13/3776
摘要： An error correction device is provided. The error correction device includes a code storage unit where a plurality of error correction codes are stored, a first error correction unit to correct a data error detected from input data by using one of a plurality of error correction codes and to output correction data, a buffer to store the correction data, and a second error correction unit to generate a new correction code from the correction data, to compare another of a plurality of error correction codes with the new correction code and to output a comparison result.
摘要翻译：提供纠错装置。误差校正装置包括存储多个纠错码的码存储单元，第一纠错单元，用于通过使用多个纠错码中的一个校正从输入数据检测到的数据错误并输出校正数据;第一纠错单元，缓冲器以存储校正数据;以及第二纠错单元，用于从校正数据生成新的校正码，将多个纠错码中的另一个与新的校正码进行比较，并输出比较结果。

3. 发明申请

US20080177938A1 Hybrid hard disk drive, computer system including the same, and flash memory DMA circuit for hybrid HDD 审中-公开
标题翻译：混合硬盘驱动器，包括相同的计算机系统和用于混合HDD的闪存DMA电路
公开(公告)号：US20080177938A1
公开(公告)日：2008-07-24
申请号：US12008930
申请日：2008-01-15
申请人： Bum-seok Yu
发明人： Bum-seok Yu
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F2212/222 , G06F2212/466 , Y02D10/13
摘要： Provided are a hybrid hard disk drive (HDD), a computer system including the hybrid HDD, and a flash memory DMA circuit for the hybrid HDD. The hybrid HDD includes a flash memory. The flash memory includes: a main memory region; and a spare memory region storing additional information necessary for transmitting user data stored in the main memory region. The flash memory DMA circuit of the hybrid HDD is used for interfacing the hybrid HDD with the flash memory. Therefore, rapid booting and low power consumption can be realized, while reducing overhead resulted from interfacing the hybrid HDD with the flash memory.
摘要翻译：提供了混合硬盘驱动器（HDD），包括混合HDD的计算机系统和用于混合HDD的闪存DMA电路。混合HDD包括闪存。闪存包括：主存储区域; 以及存储用于发送存储在主存储区域中的用户数据所需的附加信息的备用存储区域。混合HDD的闪存DMA电路用于将混合HDD与闪速存储器进行接口。因此，可以实现快速引导和低功耗，同时减少由混合HDD与闪存接口的开销。

4. 发明授权

US08316280B2 Error correcting device, method of error correction thereof, and memory device and data processing system including of the same 有权
标题翻译：误差校正装置及其纠错方法以及包括其的存储装置和数据处理系统
公开(公告)号：US08316280B2
公开(公告)日：2012-11-20
申请号：US12720903
申请日：2010-03-10
申请人： Sil Wan Chang , Bum Seok Yu , Sang Kyoo Jeong , Dong Gi Lee
发明人： Sil Wan Chang , Bum Seok Yu , Sang Kyoo Jeong , Dong Gi Lee
IPC分类号： G11C29/00
CPC分类号： H03M13/2927 , G06F11/1012 , H03M13/09 , H03M13/13 , H03M13/2906 , H03M13/37 , H03M13/3776
摘要： An error correction device is provided. The error correction device includes a code storage unit where a plurality of error correction codes are stored, a first error correction unit to correct a data error detected from input data by using one of a plurality of error correction codes and to output correction data, a buffer to store the correction data, and a second error correction unit to generate a new correction code from the correction data, to compare another of a plurality of error correction codes with the new correction code and to output a comparison result.
摘要翻译：提供纠错装置。误差校正装置包括存储多个纠错码的码存储单元，第一纠错单元，用于通过使用多个纠错码中的一个校正从输入数据检测到的数据错误并输出校正数据;第一纠错单元，缓冲器以存储校正数据;以及第二纠错单元，用于从校正数据生成新的校正码，将多个纠错码中的另一个与新的校正码进行比较，并输出比较结果。

5. 发明申请

US20100082882A1 SEMICONDUCTOR DISK DEVICES AND RELATED METHODS OF RANDOMLY ACCESSING DATA 有权
标题翻译：半导体磁盘设备和随机访问数据的相关方法
公开(公告)号：US20100082882A1
公开(公告)日：2010-04-01
申请号：US12338527
申请日：2008-12-18
申请人： Kwang-Seok Im , Bum-Seok Yu , Yang-sup Lee
发明人： Kwang-Seok Im , Bum-Seok Yu , Yang-sup Lee
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0679
摘要： A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register.
摘要翻译：计算系统包括主机，数据源设备和控制器。控制器被配置为通过设置在数据源设备中选择要访问的数据的寄存器中的信息来响应来自主机的随机访问命令。然后，控制器使用在寄存器中设置的信息连续地访问数据源设备中的数据。

6. 发明授权

US06839774B1 Single-chip data processing apparatus incorporating an electrically rewritable nonvolatile memory and method of operating the same 有权
标题翻译：并用电可重写非易失性存储器的单片数据处理装置及其操作方法
公开(公告)号：US06839774B1
公开(公告)日：2005-01-04
申请号：US09693773
申请日：2000-10-20
申请人： Jong-Keun Ahn , Bum-Seok Yu , Sang-Joo Ra , Jong-In Kim
发明人： Jong-Keun Ahn , Bum-Seok Yu , Sang-Joo Ra , Jong-In Kim
IPC分类号： G11C16/02 , G05B19/042 , G06F9/445 , G06F3/00
CPC分类号： G06F8/60 , G05B19/0426 , G05B2219/23308 , G05B2219/23345 , G05B2219/25265 , G05B2219/25341 , Y02D10/42
摘要： A microcontroller includes an electrically erasable and programmable nonvolatile memory and a memory controller for controlling the nonvolatile memory. Upon writing a control program for the microcontroller and data into the nonvolatile memory pursuant to an externally provided NVM command or an internally issued program command, a CPU of the microcontroller does not intervene in controlling the nonvolatile memory. Particularly, in a programming mode set by the external program command, CPU, buses, and communication interfaces of the microcontroller are deactivated. Further, the memory controller receives a NVM command, an address and data from outside of the microcontroller for controlling an operation of the nonvolatile memory based on the NVM command and the address without intervention of the CPU.
摘要翻译：微控制器包括电可擦除和可编程的非易失性存储器和用于控制非易失性存储器的存储器控制器。在根据外部提供的NVM命令或内部发出的程序命令将微控制器的控制程序和数据写入非易失性存储器中时，微控制器的CPU不进行非易失性存储器的控制。特别地，在由外部程序命令设置的编程模式中，微控制器的CPU，总线和通信接口被去激活。此外，存储器控制器从微控制器的外部接收NVM命令，地址和数据，用于基于NVM命令和地址来控制非易失性存储器的操作，而无需CPU的干预。

7. 发明授权

US08886956B2 Data storage apparatus having cryption and method thereof 有权
标题翻译：具有加密的数据存储装置及其方法
公开(公告)号：US08886956B2
公开(公告)日：2014-11-11
申请号：US12728325
申请日：2010-03-22
申请人： Woo-hyun Lee , Bum-seok Yu
发明人： Woo-hyun Lee , Bum-seok Yu
IPC分类号： G06F12/14 , G06F21/80 , G11B20/00 , G06F3/06
CPC分类号： G11B20/0021 , G06F3/0659 , G06F3/0679 , G06F12/1408 , G06F21/80 , G11B20/00086 , G11B20/00246 , G11B20/00507 , H04L9/0894
摘要： A storage apparatus including a storage unit to store data, a processor unit to process the data according to a command received from an external device, a key unit to store a plurality of crypto keys, and a decoder unit to select one of the crypto keys according to address information of the command received from the external device. Hardware encryption is more secure and less complex to manage.
摘要翻译：一种存储装置，包括存储数据的存储单元，处理器单元，用于根据从外部设备接收的命令来处理数据;密钥单元，用于存储多个加密密钥;以及解码器单元，用于选择所述加密密钥之一根据从外部设备接收的命令的地址信息。硬件加密更安全，管理不太复杂。

8. 发明授权

US08521946B2 Semiconductor disk devices and related methods of randomly accessing data 有权
标题翻译：半导体磁盘设备及随机访问数据的相关方法
公开(公告)号：US08521946B2
公开(公告)日：2013-08-27
申请号：US12338527
申请日：2008-12-18
申请人： Kwang-Seok Im , Bum-Seok Yu , Yang-sup Lee
发明人： Kwang-Seok Im , Bum-Seok Yu , Yang-sup Lee
IPC分类号： G06F12/00
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0679
摘要： A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register.
摘要翻译：计算系统包括主机，数据源设备和控制器。控制器被配置为通过设置在数据源设备中选择要访问的数据的寄存器中的信息来响应来自主机的随机访问命令。然后，控制器使用在寄存器中设置的信息连续地访问数据源设备中的数据。

9. 发明申请

US20090300372A1 SOLID STATE DISK AND INPUT/OUTPUT METHOD 有权
标题翻译：固态盘和输入/输出方法
公开(公告)号：US20090300372A1
公开(公告)日：2009-12-03
申请号：US12464914
申请日：2009-05-13
申请人： Woo-Hyun LEE , Ji-Soo KIM , Bum-Seok YU
发明人： Woo-Hyun LEE , Ji-Soo KIM , Bum-Seok YU
IPC分类号： G06F12/14
CPC分类号： H04L9/0637 , G06F21/79 , H04L2209/08 , H04L2209/12
摘要： Disclosed is a solid state disk including a storage unit configured to store data, and a control part configured to control enciphering and writing operation for the data using a key value and an initialization vector. The initialization vector is generated by processing an address corresponding to the data.
摘要翻译：公开了一种包括被配置为存储数据的存储单元的固态盘，以及被配置为使用键值和初始化向量来控制数据的加密和写入操作的控制部。通过处理对应于数据的地址来生成初始化向量。

10. 发明授权

US07555083B2 Synchronizing circuit for stably generating an output signal 失效
标题翻译：用于稳定地产生输出信号的同步电路
公开(公告)号：US07555083B2
公开(公告)日：2009-06-30
申请号：US10968507
申请日：2004-10-19
申请人： Bum-Seok Yu
发明人： Bum-Seok Yu
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , A61F13/38 , H04L7/0045
摘要： The present invention relates to a synchronizing circuit for stably generating an output signal irrespective of the frequency difference of clocks. According to the present invention, the synchronizing circuit receives an input signal synchronized with a first clock and then stores a state of the input signal so that the input signal is synchronized with a transition of a second clock. then, the synchronizing circuit generates an output signal synchronized with the transition of the second clock. In addition, an input signal synchronized with the first clock becomes synchronized with the second clock having a lower frequency than the first clock.
摘要翻译：本发明涉及一种用于稳定地产生输出信号的同步电路，而与时钟的频率差无关。根据本发明，同步电路接收与第一时钟同步的输入信号，然后存储输入信号的状态，使得输入信号与第二时钟的转变同步。则同步电路产生与第二时钟的转变同步的输出信号。此外，与第一时钟同步的输入信号与具有比第一时钟更低的频率的第二时钟同步。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式