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1. 发明申请

US20190149314A1 CLOCK AND DATA RECOVERY FOR PULSE BASED MULTI-WIRE LINK 审中-公开
公开(公告)号：US20190149314A1
公开(公告)日：2019-05-16
申请号：US16243647
申请日：2019-01-09
申请人： QUALCOMM Incorporated
发明人： Shoichiro Sengoku
IPC分类号： H04L7/00 , H03K5/1534 , H03K5/13 , G06F1/12 , H04L7/033 , H04L25/49 , H03K5/133
CPC分类号： H04L7/0045 , G06F1/12 , H03K5/13 , H03K5/133 , H03K5/1534 , H04L7/0037 , H04L7/0087 , H04L7/033 , H04L25/49
摘要： A method and an apparatus are provided. The apparatus may include a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.

2. 发明授权

US10014042B2 Semiconductor device 有权
公开(公告)号：US10014042B2
公开(公告)日：2018-07-03
申请号：US15481798
申请日：2017-04-07
申请人： SK hynix Inc.
发明人： Yun Gi Hong
IPC分类号： G11C7/22 , H04L7/00 , G11C7/10 , G06F13/42 , H03L7/081 , H04L7/033
CPC分类号： G11C7/222 , G06F13/4243 , G11C7/1072 , G11C7/1078 , G11C7/1093 , H03L7/0814 , H04L7/0037 , H04L7/0045 , H04L7/033
摘要： A semiconductor device includes an input/output control circuit configured to generate a first driving signal and a second driving signal by shifting a latency signal in synchronization with a clock, and generating a strobe signal which toggles according to logic levels of the first driving signal and the second driving signal; and a data input/output circuit configured to latch input data in synchronization with the strobe signal, and outputting the latched input data as output data.

3. 发明申请

US20180122441A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20180122441A1
公开(公告)日：2018-05-03
申请号：US15481798
申请日：2017-04-07
申请人： SK hynix Inc.
发明人： Yun Gi HONG
IPC分类号： G11C7/22 , H04L7/00 , G11C7/10 , G06F13/42 , H03L7/081 , H04L7/033
CPC分类号： G11C7/222 , G06F13/4243 , G11C7/1072 , G11C7/1078 , G11C7/1093 , H03L7/0814 , H04L7/0037 , H04L7/0045 , H04L7/033
摘要： A semiconductor device includes an input/output control circuit configured to generate a first driving signal and a second driving signal by shifting a latency signal in synchronization with a clock, and generating a strobe signal which toggles according to logic levels of the first driving signal and the second driving signal; and a data input/output circuit configured to latch input data in synchronization with the strobe signal, and outputting the latched input data as output data.

4. 发明申请

US20180054188A1 Low Power Adaptive Synchronizer 有权
公开(公告)号：US20180054188A1
公开(公告)日：2018-02-22
申请号：US15239217
申请日：2016-08-17
申请人： Advanced Micro Devices, Inc.
发明人： Greg Sadowski
IPC分类号： H03K3/037 , H03K19/21 , H03K5/1534
CPC分类号： H03K3/0375 , H03K5/1534 , H03K19/21 , H03K2005/00234 , H04L7/0045 , H04L7/0083
摘要： A circuit adapts to the occurrence of metastable states. The circuit inhibits passing of the metastable state to circuits that follow, by clock gating the output stage. In order to determine whether or not to gate the clock of the output stage, two detect circuits may be used. One circuit detects metastability and another circuit detects metastability resolved to a wrong logic level. The results from one or both detector circuits are used to gate the next clock cycle if needed, waiting for the metastable situation to be resolved.

5. 发明授权

US09479187B2 Predictive time-to-digital converter and method for providing a digital representation of a time interval 有权
标题翻译：用于提供时间间隔的数字表示的预测性时间 - 数字转换器和方法
公开(公告)号：US09479187B2
公开(公告)日：2016-10-25
申请号：US14568588
申请日：2014-12-12
申请人： Intel Corporation
发明人： Thomas Mayer , Stefan Tertinek
IPC分类号： H03M1/12 , H04L7/00 , H04L5/00
CPC分类号： H03M1/12 , G04F10/005 , H04L5/0048 , H04L7/0037 , H04L7/0045
摘要： Predictive time-to-digital converters (TDCs) and methods for providing a digital representation of a time interval are disclosed herein. In an example, a TDC can include a delay line, a selection circuit, and a latch circuit. The delay line can include a plurality of delay elements configured to propagate a first edge of a first signal sequentially through the plurality of delay elements. The selection circuit can be configured to receive the first signal, to receive prediction information, and to route the first signal to an input of one of the plurality of delay elements based on the prediction information. The latch circuit can receive a second signal and can latch a plurality of outputs of the delay line upon reception of a second edge of the second signal. An output of the latch circuit can provide an indication of a delay between the first edge and the second edge.
摘要翻译：这里公开了用于提供时间间隔的数字表示的预测时间 - 数字转换器（TDC）和方法。在一个示例中，TDC可以包括延迟线，选择电路和锁存电路。延迟线可以包括多个延迟元件，其被配置成顺序地通过多个延迟元件传播第一信号的第一边缘。选择电路可以被配置为基于预测信息来接收第一信号，接收预测信息，以及将第一信号路由到多个延迟元件之一的输入。锁存电路可以接收第二信号，并且可以在接收到第二信号的第二边缘时锁存延迟线的多个输出。锁存电路的输出可以提供在第一边缘和第二边缘之间的延迟的指示。

6. 发明授权

US09438253B2 High speed current mode latch 有权
标题翻译：高速电流模式锁存
公开(公告)号：US09438253B2
公开(公告)日：2016-09-06
申请号：US14727990
申请日：2015-06-02
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mustafa Ulvi Erdogan
IPC分类号： H03L7/08 , H03L7/087 , H04L7/00 , H03L7/089
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/089 , H04L7/0045
摘要： A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal.
摘要翻译：电流模式逻辑（CML）锁存器，其包括耦合到第二晶体管的第一晶体管，耦合到第四晶体管的第三晶体管，连接到第一，第二，第三和第四晶体管的第一电容器，与第一电容耦合并连接到第三和第四晶体管。第一和第二晶体管被配置为接收数据信号。第三和第四晶体管被配置为接收时钟信号。

7. 发明授权

US09419827B2 Partial response equalizer and related method 有权
公开(公告)号：US09419827B2
公开(公告)日：2016-08-16
申请号：US14865825
申请日：2015-09-25
申请人： Rambus Inc.
发明人： Chintan S. Thakkar , Kun-Yung Chang , Ting Wu
IPC分类号： H04L25/03 , H04L7/00
CPC分类号： H04L25/03057 , H04L7/0045 , H04L7/0058 , H04L7/0087 , H04L25/03063 , H04L2025/03369
摘要： A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

8. 发明申请

US20160036583A1 SYNCHRONIZATION METHOD, AND CORRESPONDING DEVICE AND INTEGRATED CIRCUIT 有权
标题翻译：同步方法和相应的器件和集成电路
公开(公告)号：US20160036583A1
公开(公告)日：2016-02-04
申请号：US14661937
申请日：2015-03-18
申请人： STMicroelectronics S.r.l.
发明人： Juri Giovannone , Valeria Bottarel , Marco Terenzi , Sandro Rossi
IPC分类号： H04L7/00
CPC分类号： H04L7/0045 , H03K5/135 , H03K5/14 , H03L7/0814 , H04L7/0037
摘要： The operation of a circuit exhibiting a delay that is subject to a time spread as a function of process, voltage, and temperature variations is synchronized with a sync signal by applying to the sync signal a digital delay, which can add to the delay that is subject to time spread.The digital delay is generated via cascaded delay elements having respective delay values and by controlling the number of cascaded delay elements in the circuit.
摘要翻译：表现出作为过程，电压和温度变化的函数的时间扩展的延迟的电路的操作与同步信号同步，该同步信号通过向同步信号施加数字延迟，这可以增加延迟受时间限制。通过具有各自的延迟值的级联延迟元件和通过控制电路中的级联延迟元件的数量来产生数字延迟。

9. 发明申请

US20150349786A1 HIGH SPEED CURRENT MODE LATCH 有权
标题翻译：高速电流模式锁
公开(公告)号：US20150349786A1
公开(公告)日：2015-12-03
申请号：US14727990
申请日：2015-06-02
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mustafa Ulvi ERDOGAN
IPC分类号： H03L7/08 , H04L7/00 , H03L7/087
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/089 , H04L7/0045
摘要： A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal.
摘要翻译：电流模式逻辑（CML）锁存器，其包括耦合到第二晶体管的第一晶体管，耦合到第四晶体管的第三晶体管，连接到第一，第二，第三和第四晶体管的第一电容器，与第一电容耦合并连接到第三和第四晶体管。第一和第二晶体管被配置为接收数据信号。第三和第四晶体管被配置为接收时钟信号。

10. 发明授权

US09197397B1 Flip-flop-based clock deskew circuit 有权
标题翻译：基于触发器的时钟偏移电路
公开(公告)号：US09197397B1
公开(公告)日：2015-11-24
申请号：US14329272
申请日：2014-07-11
申请人： Oracle International Corporation
发明人： Tarik Ono , Suwen Yang , Mark R. Greenstreet
IPC分类号： H04L7/00
CPC分类号： H04L7/0012 , G06F1/10 , G06F1/12 , H04L7/0037 , H04L7/0045
摘要： A clock deskew circuit for transferring data from a first clock domain to a second clock domain. This circuit includes a data path, which has: a transmitter latch controlled by a transmitter clock in a first clock domain; a receiver latch controlled by a receiver clock in a second clock domain; and an intermediate latch coupled between the transmitter latch and the receiver latch. The transmitter clock and the receiver clock have an unknown phase offset. The circuit additionally includes a control circuit coupled between the transmitter clock and the receiver clock, and generates a control clock for the immediate latch based on the transmitter clock and the receiver clock. The control circuit selects between a first operation mode and a second operation mode for the data path circuit based at least on the phase relationship of the control clock with respect to the transmitter clock and the receiver clock.
摘要翻译：一种用于将数据从第一时钟域传送到第二时钟域的时钟解调电路。该电路包括数据路径，其具有：由第一时钟域中的发射机时钟控制的发射机锁存器; 由第二时钟域中的接收器时钟控制的接收器锁存器; 以及耦合在发射机锁存器和接收器锁存器之间的中间锁存器。发射机时钟和接收机时钟具有未知的相位偏移。电路还包括耦合在发射机时钟和接收机时钟之间的控制电路，并且基于发射机时钟和接收机时钟产生用于立即锁存器的控制时钟。控制电路至少基于控制时钟相对于发射机时钟和接收机时钟的相位关系在数据路径电路的第一操作模式和第二操作模式之间进行选择。

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