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1. 发明申请

US20070085140A1 One transistor memory cell having strained electrically floating body region, and method of operating same 审中-公开
标题翻译：具有应变电浮动体区域的一个晶体管存储单元及其操作方法
公开(公告)号：US20070085140A1
公开(公告)日：2007-04-19
申请号：US11580169
申请日：2006-10-12
申请人： Cedric Bassin
发明人： Cedric Bassin
IPC分类号： H01L27/12
CPC分类号： H01L29/7841 , H01L27/108 , H01L27/10802
摘要： A semiconductor memory cell comprising a transistor having (i) an electrically floating body region and (ii) semiconductor source, drain and/or body regions that are “locally” or “globally” under mechanical strain (for example, strain introduced via tensile or compressive forces). The semiconductor memory cell includes (1) a first data state which corresponds to a first charge in the electrically floating body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the electrically floating body region of the transistor of the memory cell. The semiconductor memory cell may comprise a portion of an integrated circuit device, for example, logic device (such as, a microcontroller or microprocessor) or a portion of a memory device (such as, a discrete memory). A plurality of such memory cells may be arranged to form a memory cell array.
摘要翻译：一种半导体存储单元，包括晶体管，其具有（i）电浮动体区域和（ii）在机械应变（例如通过拉伸或拉伸或拉伸）引入的应变的情况下“局部地”或“全局地”的半导体源，漏极和/或主体区域压缩力）。半导体存储单元包括（1）对应于存储单元的晶体管的电浮体区域中的第一电荷的第一数据状态，和（2）对应于电浮置中的第二电荷的第二数据状态存储单元晶体管的体区。半导体存储单元可以包括集成电路器件的一部分，例如逻辑器件（诸如微控制器或微处理器）或存储器件（例如，分立存储器）的一部分。可以布置多个这样的存储单元以形成存储单元阵列。

2. 发明授权

US08085594B2 Reading technique for memory cell with electrically floating body transistor 有权
标题翻译：具有电浮体晶体管的存储单元的读取技术
公开(公告)号：US08085594B2
公开(公告)日：2011-12-27
申请号：US12130011
申请日：2008-05-30
申请人： Serguei Okhonin , Mikhail Nagoga , Cedric Bassin
发明人： Serguei Okhonin , Mikhail Nagoga , Cedric Bassin
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该器件包括基本上由一个晶体管组成的存储单元。晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。该装置包括耦合到该存储单元的数据检测电路。数据检测电路包括耦合到栅极区域的字线和耦合到源极区域或漏极区域的位输出。

3. 发明授权

US08659948B2 Techniques for reading a memory cell with electrically floating body transistor 有权
标题翻译：用电浮体晶体管读取存储单元的技术
公开(公告)号：US08659948B2
公开(公告)日：2014-02-25
申请号：US13336805
申请日：2011-12-23
申请人： Serguei Okhonin , Mikhail Nagoga , Cedric Bassin
发明人： Serguei Okhonin , Mikhail Nagoga , Cedric Bassin
IPC分类号： G11C16/04
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该器件包括基本上由一个晶体管组成的存储单元。晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。该装置包括耦合到该存储单元的数据检测电路。数据检测电路包括耦合到栅极区域的字线和耦合到源极区域或漏极区域的位输出。

4. 发明申请

US20120092942A1 TECHNIQUES FOR READING A MEMORY CELL WITH ELECTRICALLY FLOATING BODY TRANSISTOR 有权
标题翻译：用于读取具有电浮标体晶体管的存储器单元的技术
公开(公告)号：US20120092942A1
公开(公告)日：2012-04-19
申请号：US13336805
申请日：2011-12-23
申请人： SERGUEI OKHONIN , Mikhail Nagoga , Cedric Bassin
发明人： SERGUEI OKHONIN , Mikhail Nagoga , Cedric Bassin
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该器件包括基本上由一个晶体管组成的存储单元。晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。该装置包括耦合到该存储单元的数据检测电路。数据检测电路包括耦合到栅极区域的字线和耦合到源极区域或漏极区域的位输出。

5. 发明申请

US20090016101A1 Reading Technique for Memory Cell With Electrically Floating Body Transistor 有权
标题翻译：具有电浮体晶体管的存储单元的读取技术
公开(公告)号：US20090016101A1
公开(公告)日：2009-01-15
申请号：US12130011
申请日：2008-05-30
申请人： Serguei Okhonin , Mikhail Nagoga , Cedric Bassin
发明人： Serguei Okhonin , Mikhail Nagoga , Cedric Bassin
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该器件包括基本上由一个晶体管组成的存储单元。晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。该装置包括耦合到该存储单元的数据检测电路。数据检测电路包括耦合到栅极区域的字线和耦合到源极区域或漏极区域的位输出。

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