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1. 发明授权

US09093169B2 Nonvolatile semiconductor memory apparatus and data sensing method thereof 有权
标题翻译：非易失性半导体存储装置及其数据检测方法
公开(公告)号：US09093169B2
公开(公告)日：2015-07-28
申请号：US13584990
申请日：2012-08-14
申请人： Chang Won Yang , Hwang Huh
发明人： Chang Won Yang , Hwang Huh
IPC分类号： G11C16/28 , G11C11/24 , G11C7/04 , G11C7/08 , G11C7/10 , G11C11/56
CPC分类号： G11C11/24 , G11C7/04 , G11C7/08 , G11C7/106 , G11C11/5642 , G11C16/28
摘要： A nonvolatile semiconductor memory apparatus includes a memory cell block, a plurality of page buffers, and a reference page buffer unit. The memory cell block includes a plurality of memory cell strings each of which includes a plurality of memory cells and a dummy memory cell string which includes a plurality of dummy memory cells. The page buffers sense data stored in the memory cells and apply the sensed data to an output node. The reference page buffer unit senses the dummy memory cells and adjusts the timing to apply the values sensed by the page buffers to the output node.
摘要翻译：非易失性半导体存储装置包括存储单元块，多个页缓冲器和参考页缓冲单元。存储单元块包括多个存储单元串，每个存储单元串包括多个存储单元和包括多个虚拟存储单元的虚拟存储单元串。页缓冲器感测存储在存储单元中的数据，并将感测数据应用于输出节点。参考页面缓冲器单元感测虚拟存储器单元并且调整定时以将由页面缓冲器感测的值应用于输出节点。

2. 发明授权

US08929155B2 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08929155B2
公开(公告)日：2015-01-06
申请号：US13183641
申请日：2011-07-15
申请人： Byoung Sung Yoo , Chang Won Yang
发明人： Byoung Sung Yoo , Chang Won Yang
IPC分类号： G11C7/10 , G11C16/04
CPC分类号： G11C16/0483 , G11C2216/14
摘要： A semiconductor memory device includes memory cells for storing data, page buffers each configured to comprise a dynamic latch and a static latch on which data to be programmed in to the memory cells or data read from the memory cells are latched, and a control logic configured to store a plurality of refresh mode select codes corresponding to various refresh cycles, and refresh the dynamic latch by exchanging data between the static latch and the dynamic latch according to a refresh cycle corresponding to a selected refresh mode select code.
摘要翻译：半导体存储器件包括用于存储数据的存储器单元，每个被配置为包括动态锁存器和静态锁存器的页缓冲器，在其上锁存要被编程到存储器单元的数据或从存储器单元读取的数据的静态锁存器，以及配置存储对应于各种刷新周期的多个刷新模式选择代码，并且根据对应于所选择的刷新模式选择代码的刷新周期，通过在静态锁存器和动态锁存器之间交换数据来刷新动态锁存器。

3. 发明申请

US20130163343A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20130163343A1
公开(公告)日：2013-06-27
申请号：US13600541
申请日：2012-08-31
申请人： Chang Won YANG , Hwang Huh , Myung jin Park , Chang Hyuk Lee
发明人： Chang Won YANG , Hwang Huh , Myung jin Park , Chang Hyuk Lee
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C16/26
摘要： The semiconductor memory device includes a memory cell array that includes a plurality of cell strings coupled between a common source line and a plurality of bit lines, a peripheral circuit that reads data stored in a selected memory cell, a bouncing detection circuit that compares a voltage supplied to the common source line and a reference voltage to thereby output a detection signal while performing a reading operation, and a control circuit that controls the peripheral circuit in order to perform the reading operation by adjusting the number of sensing operation times in accordance with the detection signal.
摘要翻译：半导体存储器件包括存储单元阵列，其包括耦合在公共源极线和多个位线之间的多个单元串，读出存储在选择的存储单元中的数据的外围电路，将电压提供给公共源极线和参考电压，从而在执行读取操作时输出检测信号;以及控制电路，其控制外围电路，以便根据所述控制电路来调整感测操作次数，从而执行读取操作检测信号。

4. 发明申请

US20120314506A1 SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体器件及其操作方法
公开(公告)号：US20120314506A1
公开(公告)日：2012-12-13
申请号：US13492286
申请日：2012-06-08
申请人： Kwang Ho BAEK , Jin Su PARK , Chang Won YANG
发明人： Kwang Ho BAEK , Jin Su PARK , Chang Won YANG
IPC分类号： G11C16/10
CPC分类号： G11C7/12 , G11C11/5628 , G11C16/0483 , G11C16/24
摘要： A semiconductor device includes cell strings that each include a plurality of memory cells, a page buffer having latches coupled to bit lines and precharge the bit lines in response to page buffer control signals, a page buffer control circuit configured to generate the page buffer control signals using a high voltage source, and a controller configured to generate control signals for controlling the page buffer control circuit.
摘要翻译：半导体器件包括每个包括多个存储器单元的单元串，具有耦合到位线的锁存器并响应于页缓冲器控制信号对位线进行预充电的页缓冲器，被配置为生成页缓冲器控制信号的页缓冲器控制电路使用高电压源和被配置为产生用于控制页面缓冲器控制电路的控制信号的控制器。

5. 发明申请

US20120294093A1 SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：半导体器件及其工作方法
公开(公告)号：US20120294093A1
公开(公告)日：2012-11-22
申请号：US13471550
申请日：2012-05-15
申请人： Chang Won YANG
发明人： Chang Won YANG
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/32
摘要： An operating method of a semiconductor device includes precharging bit lines corresponding to selected memory cells, supplying a first verify voltage to a word line coupled to the selected memory cells and outputting programming states of the selected memory cells to the bit lines during a first time period, sensing potentials of the bit lines that have the programming states of the selected memory cells outputted to the bit lines during the first time period, supplying a first target voltage higher than the first verify voltage to the word line and outputting programming states of the selected memory cells to the bit lines during a second time period shorter than the first time period, and sensing potentials of the bit lines that have the programming states of the selected memory cells outputted to the bit lines during the second time period.
摘要翻译：半导体器件的操作方法包括对与所选择的存储器单元相对应的预充电位线，向耦合到所选择的存储器单元的字线提供第一验证电压，并且在第一时间周期期间将所选择的存储器单元的编程状态输出到位线，在第一时间段期间感测具有输出到位线的所选存储单元的编程状态的位线的电位，将高于第一验证电压的第一目标电压提供给字线并输出所选择的编程状态在比第一时间段短的第二时间段期间将存储器单元存储到位线，以及感测在第二时间段期间具有输出到位线的所选存储单元的编程状态的位线的电位。

6. 发明申请

US20110157998A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20110157998A1
公开(公告)日：2011-06-30
申请号：US12982434
申请日：2010-12-30
申请人： Chang Won YANG
发明人： Chang Won YANG
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/10 , G11C16/3454 , G11C16/3459
摘要： A method of operating a semiconductor memory device comprises performing a third program such that threshold voltages of third memory cells, from among memory cells of a selected page, are higher than a third level, after the third program loop is completed, performing a second program loop such that threshold voltages of second memory cells, from among the memory cells, are lower than the third level, but higher than a second level, and after the second program loop is completed, performing a first program loop such that threshold voltages of first memory cells, from among the memory cells, are lower than the second level, but higher than a first level.
摘要翻译：一种操作半导体存储器件的方法包括执行第三程序，使得在第三程序循环完成之后，从所选页的存储单元中的第三存储器单元的阈值电压高于第三电平，执行第二程序使得来自存储器单元的第二存储器单元的阈值电压低于第三电平但高于第二电平，并且在第二程序循环完成之后，执行第一程序循环，使得阈值电压为第一来自存储器单元的存储单元低于第二级，但高于第一级。

7. 发明申请

US20100329005A1 SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF 有权
标题翻译：半导体存储器件及其编程方法
公开(公告)号：US20100329005A1
公开(公告)日：2010-12-30
申请号：US12827077
申请日：2010-06-30
申请人： Chang Won YANG
发明人： Chang Won YANG
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5621 , G11C2216/14
摘要： A programming method comprised of: classifying memory cells to be programmed into first, second and third levels; applying a program inhibition voltage to an unselected bit line, applying a ground voltage to bit lines, which are coupled with memory cells that are to be programmed into the third level, among selected bit lines, and applying a first voltage, which is lower than the program inhibition voltage but higher than a ground voltage, to bit lines coupled with memory cells that are to be programmed into the second level, and applying a second voltage, which is lower than the program inhibition voltage but higher than the first voltage, to bit line coupled with memory cells that are to be programmed into the first level; and supplying a program voltage, which gradually increases, to a selected word line coupled with the memory cells while applying the voltages to the bit lines.
摘要翻译：一种编程方法，包括：将要编程的存储器单元分类为第一级，第二级和第三级; 将程序禁止电压施加到未选择的位线，对选择的位线中的与要编程到第三电平的存储器单元耦合的位线施加接地电压，并施加低于第一电压的第一电压程序禁止电压但高于接地电压，与要编程到第二电平的存储器单元耦合的位线，以及施加低于编程禁止电压但高于第一电压的第二电压到与要被编程到第一级的存储器单元耦合的位线; 并且在向位线施加电压的同时，向与所述存储单元耦合的选定字线提供逐渐增加的编程电压。

8. 发明授权

US07706190B2 Method of program-verifying a nonvolatile memory device using subdivided verifications with increasing verify voltages 失效
标题翻译：使用增加的验证电压的细分验证对非易失性存储器件进行程序验证的方法
公开(公告)号：US07706190B2
公开(公告)日：2010-04-27
申请号：US12163921
申请日：2008-06-27
申请人： Chang Won Yang , Jong Hyun Wang , Se Chun Park
发明人： Chang Won Yang , Jong Hyun Wang , Se Chun Park
IPC分类号： G11C16/34
CPC分类号： G11C16/3454 , G11C11/5628 , G11C16/3459 , G11C2211/5621
摘要： In a method of operating a non-volatile memory device subdivided verifications are performed by increasing verify voltages. Accordingly, threshold voltage distributions of memory cells can be narrowed and, therefore, the program performance of a flash memory device can be improved.
摘要翻译：在操作非易失性存储器装置的方法中，通过增加验证电压来执行细分验证。因此，存储器单元的阈值电压分布可以变窄，因此可以提高闪速存储器件的程序性能。

9. 发明申请

US20080205138A1 MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：存储器件及其操作方法
公开(公告)号：US20080205138A1
公开(公告)日：2008-08-28
申请号：US11966007
申请日：2007-12-28
申请人： Jong Hyun Wang , Duck Ju Kim , Seong Hun Park , Chang Won Yang
发明人： Jong Hyun Wang , Duck Ju Kim , Seong Hun Park , Chang Won Yang
IPC分类号： G11C16/06 , G11C7/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array.
摘要翻译：存储器件具有多层单元（MLC）的存储单元。存储单元阵列包括多个单元串，每个串提供在位线和公共源极线之间，其中在编程验证时将正电压施加到公共源极线。页面缓冲器被配置为对MLC进行编程，读取存储器单元并执行程序验证。通过顺序地增加位线选择信号的电压电平直到位线选择信号达到足以验证存储单元阵列中选定单元的编程状态的电压来执行该程序验证。

10. 发明申请

US20080158987A1 NON-VOLATILE MEMORY DEVICE AND DATA READ METHOD AND PROGRAM VERIFY METHOD OF NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件和非易失性存储器件的数据读取方法和程序验证方法
公开(公告)号：US20080158987A1
公开(公告)日：2008-07-03
申请号：US11751016
申请日：2007-05-19
申请人： Seong Hun PARK , Duck Ju KIM , Chang Won YANG
发明人： Seong Hun PARK , Duck Ju KIM , Chang Won YANG
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/24 , G11C16/3454
摘要： A non-volatile memory device includes an even bit line and an odd bit line, a first register, a second register, a first precharge unit, a second precharge unit and a bit line select unit. The even bit line and the odd bit line are connected to a memory cell array. The first register is connected to the even bit line and configured to store specific data. The second register is connected to the odd bit line and configured to store specific data. The first precharge unit precharges an even sense node, formed at a node of the even bit line and the first register, with a high level or supplies supplementary current to the even sense node. The second precharge unit precharges an odd sense node, formed at a node of the odd bit line and the second register, with a high level or supplies supplementary current to the odd sense node. The bit line select unit connects the even bit line and the even sense node and connects the odd bit line and the odd sense node.
摘要翻译：非易失性存储器件包括偶数位线和奇数位线，第一寄存器，第二寄存器，第一预充电单元，第二预充电单元和位线选择单元。偶数位线和奇数位线连接到存储单元阵列。第一个寄存器连接到偶数位线，并配置为存储特定数据。第二个寄存器连接到奇数位线，并配置为存储特定数据。第一预充电单元以偶数位线和第一寄存器的一个节点对偶数感测节点进行预充电，或者将高电平提供给偶校验节点。第二预充电单元以奇数位线和第二寄存器的节点处形成的奇数检测节点以高电平预充电，或者向奇检测节点提供辅助电流。位线选择单元连接偶数位线和偶数检测节点，并连接奇数位线和奇数检测节点。

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