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1. 发明授权

US08080886B2 Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same 有权
标题翻译：具有覆盖键和对准键的集成电路半导体器件及其制造方法
公开(公告)号：US08080886B2
公开(公告)日：2011-12-20
申请号：US12111651
申请日：2008-04-29
申请人： Chang-Jin Kang , Myeong-Cheol Kim , Man-Hyoung Ryoo , Si-Hyeung Lee , Doo-Youl Lee
发明人： Chang-Jin Kang , Myeong-Cheol Kim , Man-Hyoung Ryoo , Si-Hyeung Lee , Doo-Youl Lee
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.
摘要翻译：一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案硅衬底和形成在第一绝缘图案上的第一导电图案。覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案第二掩埋绝缘层和第三沟槽。

2. 发明授权

US07531449B2 Method of forming fine patterns using double patterning process 有权
标题翻译：使用双重图案化工艺形成精细图案的方法
公开(公告)号：US07531449B2
公开(公告)日：2009-05-12
申请号：US11730264
申请日：2007-03-30
申请人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
发明人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
IPC分类号： H01L21/4763
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.
摘要翻译：公开了一种在形成在基板上的材料层中形成多个接触孔的双重图案方法。该方法形成在材料层上沿第一方向以第一间距分开的平行多个第一硬掩模图案，与第一硬掩模图案交错并与第一硬掩模分离的自对准并行多个第二硬掩模图案通过缓冲层形成图案以形成复合掩模图案，以及与第一方向相交的第二方向的多个上掩模图案，以与复合掩模图案一起掩蔽缓冲层的选定部分。然后，该方法使用复合硬掩模图案和上掩模图案作为蚀刻掩模蚀刻缓冲层的未选择部分，以形成暴露材料层的选定部分的多个硬掩模孔，然后蚀刻所选择的部分所述材料层形成所述多个接触孔。

3. 发明授权

US07479445B2 Methods of forming field effect transistors having t-shaped gate electrodes using carbon-based etching masks 有权
标题翻译：使用碳基蚀刻掩模形成具有t形栅电极的场效应晶体管的方法
公开(公告)号：US07479445B2
公开(公告)日：2009-01-20
申请号：US11247937
申请日：2005-10-11
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
IPC分类号： H01L21/28 , H01L21/335
CPC分类号： H01L29/1037 , H01L21/823437 , H01L21/823456 , H01L29/76
摘要： Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.
摘要翻译：形成场效应晶体管的方法包括在半导体衬底的表面上形成主要包含碳的第一电绝缘层，并且图案化第一电绝缘层以在其中限定开口。通过使用图案化的第一电绝缘层作为蚀刻掩模蚀刻衬底的表面，在衬底中形成沟槽。沟槽填充有栅电极。第一电绝缘层在含有氧的环境中被图案化。当这种含氧环境通过第一电绝缘层内的开口露出时，支撑衬底内基于沟槽的隔离区的进一步氧化。

4. 发明申请

US20090008701A1 NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090008701A1
公开(公告)日：2009-01-08
申请号：US11555126
申请日：2006-10-31
申请人： Dong-Hyun KIM , Gyung-Jin MIN , Chang-Jin KANG , Seung-Pil CHUNG
发明人： Dong-Hyun KIM , Gyung-Jin MIN , Chang-Jin KANG , Seung-Pil CHUNG
IPC分类号： H01L29/00 , H01L21/3205
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/517
摘要： A nonvolatile memory device includes a semiconductor substrate, a charge trap layer formed on the semiconductor substrate, a blocking layer formed on the charge trap layer, and a gate electrode formed on the blocking layer. Sides of blocking layer extend laterally beyond sides of the charge trap layer and lateral sides of the gate electrode.
摘要翻译：非易失性存储器件包括半导体衬底，形成在半导体衬底上的电荷阱层，形成在电荷陷阱层上的阻挡层和形成在阻挡层上的栅电极。阻挡层的侧面横向延伸超过电荷陷阱层的侧面和栅电极的侧边。

5. 发明授权

US07384843B2 Method of fabricating flash memory device including control gate extensions 失效
标题翻译：包括控制门扩展的闪存设备的制造方法
公开(公告)号：US07384843B2
公开(公告)日：2008-06-10
申请号：US11260377
申请日：2005-10-28
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Pil Chung
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11521
摘要： A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.
摘要翻译：制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。

6. 发明授权

US07381508B2 Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same 有权
标题翻译：具有覆盖键和对准键的集成电路半导体器件及其制造方法
公开(公告)号：US07381508B2
公开(公告)日：2008-06-03
申请号：US10867468
申请日：2004-06-14
申请人： Chang-Jin Kang , Myeong-Cheol Kim , Man-Hyoung Ryoo , Si-Hyeung Lee , Doo-Youl Lee
发明人： Chang-Jin Kang , Myeong-Cheol Kim , Man-Hyoung Ryoo , Si-Hyeung Lee , Doo-Youl Lee
IPC分类号： G03F9/00 , G03F7/20
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.
摘要翻译：一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案硅衬底和形成在第一绝缘图案上的第一导电图案。覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案第二掩埋绝缘层和第三沟槽。

7. 发明申请

US20070287299A1 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20070287299A1
公开(公告)日：2007-12-13
申请号：US11711781
申请日：2007-02-28
申请人： Doo-youl Lee , Suk-joo Lee , Yool Kang , Han-ku Cho , Chang-jin Kang , Jae-ok Yoo , Sung-chan Park
发明人： Doo-youl Lee , Suk-joo Lee , Yool Kang , Han-ku Cho , Chang-jin Kang , Jae-ok Yoo , Sung-chan Park
IPC分类号： H01L21/266
CPC分类号： H01L21/0337
摘要： A method of forming a semiconductor device includes forming a first mask pattern on a target layer, the first mask pattern exposing a first portion of the target layer, forming an intermediate material layer, including depositing an intermediate material layer film on a side of the first mask pattern and the first portion of the target layer, and thinning the intermediate material layer film to form the intermediate material layer, forming a second mask pattern that exposes a second portion of the intermediate material layer, removing the exposed second portion of the intermediate material layer to expose the target layer, and patterning the target layer using the first and second mask patterns as patterning masks.
摘要翻译：形成半导体器件的方法包括：在目标层上形成第一掩模图案，第一掩模图案暴露目标层的第一部分，形成中间材料层，包括在第一掩模图案的一侧上沉积中间材料层膜掩模图案和目标层的第一部分，并且使中间材料层膜变薄以形成中间材料层，形成暴露中间材料层的第二部分的第二掩模图案，去除中间材料的暴露的第二部分层以露出目标层，以及使用第一和第二掩模图案作为图案掩模来图案化目标层。

8. 发明授权

US07291531B2 Method of fabricating semiconductor device having capacitor 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US07291531B2
公开(公告)日：2007-11-06
申请号：US11048995
申请日：2005-02-02
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层电极在下电极上。

9. 发明授权

US07256143B2 Semiconductor device having self-aligned contact plug and method for fabricating the same 有权
标题翻译：具有自对准接触插塞的半导体器件及其制造方法
公开(公告)号：US07256143B2
公开(公告)日：2007-08-14
申请号：US11058670
申请日：2005-02-15
申请人： Myeong-Cheol Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Young Son
发明人： Myeong-Cheol Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Young Son
IPC分类号： H01L21/31
CPC分类号： H01L21/76831 , H01L21/76897 , H01L23/5226 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.
摘要翻译：提供一种具有自对准接触插塞的半导体器件和制造半导体器件的方法。半导体器件包括导电图案，第一层间绝缘层，第一间隔物，第二层间绝缘层和接触塞。在每个导电图案中，导电层和覆盖层依次沉积在半导体衬底上的绝缘层上。第一层间绝缘层填充导电图案之间的空间，并且具有这样的高度，使得当第一层间绝缘层放置在绝缘层上时，第一层间绝缘层低于封盖层的顶表面，但高于顶部导电层的表面。第一间隔件包围第一层间绝缘层上的覆盖层的外表面。第二层间绝缘层覆盖第一层间绝缘层，覆盖层和第一间隔物，并且具有平坦化的顶表面。接触插塞穿过第二层间绝缘层，第一层间绝缘层和导电图案之间的绝缘层电连接到半导体衬底，具有由第二间隔物包围的外壁，并且与盖层

10. 发明申请

US20060293781A1 Method of optimizing seasoning recipe for etch process 审中-公开
公开(公告)号：US20060293781A1
公开(公告)日：2006-12-28
申请号：US11510987
申请日：2006-08-28
申请人： Hong Cho , Chang-Jin Kang , Kyeong-Koo Chi , Cheol-Kyu Lee , Hye-Jin Jo
发明人： Hong Cho , Chang-Jin Kang , Kyeong-Koo Chi , Cheol-Kyu Lee , Hye-Jin Jo
IPC分类号： G06F19/00
CPC分类号： H01L21/67253 , H01L21/32137 , H01L21/67069 , H01L22/20
摘要： A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.

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