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1. 发明授权

US08551759B2 Oligomer probe array and method of producing the same 失效
标题翻译：低聚物探针阵列及其制备方法
公开(公告)号：US08551759B2
公开(公告)日：2013-10-08
申请号：US11686506
申请日：2007-03-15
申请人： Jung-hwan Hah , Sung-min Chi , Kyoung-seon Kim , Won-sun Kim , Han-ku Cho , Sang-jun Choi , Man-hyoung Ryoo
发明人： Jung-hwan Hah , Sung-min Chi , Kyoung-seon Kim , Won-sun Kim , Han-ku Cho , Sang-jun Choi , Man-hyoung Ryoo
IPC分类号： C12M1/00 , C12M1/34 , C12Q1/68 , G01N33/53 , G01N33/551 , G01N33/552 , G01N33/545 , C07H21/02
CPC分类号： C12Q1/6834 , C12Q2563/155
摘要： An oligomer probe array having improved reaction yield is provided. The oligomer probe array includes a substrate, an immobilization layer on the substrate, a plurality of nano particles coupled with a surface of the immobilization layer, and a plurality of oligomer probes coupled with surfaces of the nano particles.
摘要翻译：提供了具有改善的反应产率的低聚物探针阵列。低聚物探针阵列包括基底，基底上的固定层，与固定层的表面耦合的多个纳米颗粒以及与纳米颗粒表面结合的多个低聚物探针。

2. 发明授权

US07842450B2 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US07842450B2
公开(公告)日：2010-11-30
申请号：US11711781
申请日：2007-02-28
申请人： Doo-youl Lee , Suk-joo Lee , Yool Kang , Han-ku Cho , Chang-jin Kang , Jae-ok Yoo , Sung-chan Park
发明人： Doo-youl Lee , Suk-joo Lee , Yool Kang , Han-ku Cho , Chang-jin Kang , Jae-ok Yoo , Sung-chan Park
IPC分类号： G03F7/00
CPC分类号： H01L21/0337
摘要： A method of forming a semiconductor device includes forming a first mask pattern on a target layer, the first mask pattern exposing a first portion of the target layer, forming an intermediate material layer, including depositing an intermediate material layer film on a side of the first mask pattern and the first portion of the target layer, and thinning the intermediate material layer film to form the intermediate material layer, forming a second mask pattern that exposes a second portion of the intermediate material layer, removing the exposed second portion of the intermediate material layer to expose the target layer, and patterning the target layer using the first and second mask patterns as patterning masks.
摘要翻译：形成半导体器件的方法包括：在目标层上形成第一掩模图案，第一掩模图案暴露目标层的第一部分，形成中间材料层，包括在第一掩模图案的一侧上沉积中间材料层膜掩模图案和目标层的第一部分，并且使中间材料层膜变薄以形成中间材料层，形成暴露中间材料层的第二部分的第二掩模图案，去除中间材料的暴露的第二部分层以露出目标层，以及使用第一和第二掩模图案作为图案掩模来图案化目标层。

3. 发明授权

US07795099B2 Semiconductor devices having Fin-type active areas and methods of manufacturing the same 有权
标题翻译：具有Fin型有源区的半导体器件及其制造方法
公开(公告)号：US07795099B2
公开(公告)日：2010-09-14
申请号：US11979748
申请日：2007-11-08
申请人： Hyun-jae Kang , Ji-young Lee , Han-ku Cho , Gi-sung Yeo
发明人： Hyun-jae Kang , Ji-young Lee , Han-ku Cho , Gi-sung Yeo
IPC分类号： H01L21/762
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A semiconductor device having a fin type active area includes a plurality of active regions, a first device isolation layer and a recessed second device isolation layer disposed in a direction of gate electrodes of the semiconductor device. A recessed second device isolation layer and a first device isolation layer are disposed in a vertical direction of the gate electrodes. The first device isolation layer and the plurality of active regions are alternately disposed in a first direction of the plurality of active regions.
摘要翻译：具有翅片型有源区的半导体器件包括沿着半导体器件的栅电极的方向设置的多个有源区，第一器件隔离层和凹陷的第二器件隔离层。凹陷的第二器件隔离层和第一器件隔离层设置在栅电极的垂直方向上。第一器件隔离层和多个有源区交替地设置在多个有源区的第一方向上。

4. 发明授权

US07787301B2 Flash memory device using double patterning technology and method of manufacturing the same 有权
标题翻译：使用双重图案化技术的闪存器件及其制造方法
公开(公告)号：US07787301B2
公开(公告)日：2010-08-31
申请号：US11590207
申请日：2006-10-31
申请人： Doo-youl Lee , Han-ku Cho , Suk-joo Lee , Gi-sung Yeo , Cha-won Koh , Pan-suk Kwak
发明人： Doo-youl Lee , Han-ku Cho , Suk-joo Lee , Gi-sung Yeo , Cha-won Koh , Pan-suk Kwak
IPC分类号： G11C16/06
CPC分类号： H01L27/11531 , H01L27/11526
摘要： Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.
摘要翻译：提供一种闪速存储器件及其制造方法。闪存设备包括字符串。串中的每一个具有字符串选择线，接地选择线和在串选择线和地选择线之间形成的奇数个字线。

5. 发明申请

US20090218609A1 Semiconductor Memory Devices Including Offset Bit Lines 有权
标题翻译：包括偏移位线的半导体存储器件
公开(公告)号：US20090218609A1
公开(公告)日：2009-09-03
申请号：US12465202
申请日：2009-05-13
申请人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
发明人： Doo-Hoon Goo , Han-Ku Cho , Joo-Tae Moon , Sang-Gyun Woo , Gi-Sung Yeo , Kyoung-Yun Baek
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10882 , H01L27/11502
摘要： A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.
摘要翻译：半导体存储器件可以包括具有多个有源区的衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。长度可以大于宽度，并且多个有源区可以在第二轴的方向上设置在多个有效区列中。可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。衬底上的多个位线可以跨过多个字线对，每个位线电耦合到每个列的有源区的相应漏极部分，并且每个位线布置在相应的漏极部分和另一个漏极部分的另一个漏极部分之间相同列的相邻有效区域。

6. 发明授权

US07378196B2 Method of manufacturing mask for correcting optical proximity effect 失效
标题翻译：制造用于校正光学邻近效应的掩模的方法
公开(公告)号：US07378196B2
公开(公告)日：2008-05-27
申请号：US10982813
申请日：2004-11-08
申请人： Byeong-Soo Kim , Han-ku Cho
发明人： Byeong-Soo Kim , Han-ku Cho
IPC分类号： G03F1/00
CPC分类号： G03F1/34 , G03F1/29 , G03F1/36 , G03F7/70441
摘要： A mask corrects for an optical proximity effect (OPE). A dummy pattern having a phase-edge effect is formed on a mask substrate. The phase-edge effect reduces the intensity of light at the boundary of two transmitting regions from through transmitted light has a phase difference. A pattern can then be formed in a photolithographic process using the phase-edge effect. A difference between “isolated” and “dense” patterns formed on a wafer can be reduced by forming a dummy pattern in an isolated pattern region of the mask and making the diffraction pattern of the isolated pattern the same as that of the dense pattern, thereby improving the total focus margin. Because the intensity of light is reduced at the boundary between a first region in which the phase of the transmitted light is 0° and a second region in which the phase of the transmitted light is 180°, for example, a photoresist layer is not photosensitized.
摘要翻译：掩模校正光学邻近效应（OPE）。在掩模基板上形成具有相边效应的虚设图案。相位效应通过透射光降低两个透射区域的边界处的光强度，具有相位差。然后可以使用相缘效应在光刻工艺中形成图案。可以通过在掩模的隔离图案区域中形成虚设图案并使孤立图案的衍射图案与致密图案相同，从而可以减小在晶片上形成的“隔离”和“密集”图案之间的差异，由此提高总焦距。因为在透射光的相位为0°的第一区域和透射光的相位为180°的第二区域之间的边界处的光的强度例如光致抗蚀剂层不被光敏化。

7. 发明授权

US07344999B2 Method for cleaning substrate having exposed silicon and silicon germanium layers and related method for fabricating semiconductor device 有权
标题翻译：用于清洁具有暴露的硅和锗锗层的衬底的方法和用于制造半导体器件的相关方法
公开(公告)号：US07344999B2
公开(公告)日：2008-03-18
申请号：US11527473
申请日：2006-09-27
申请人： Chang-Sup Mun , Woo-Gwan Shim , Han-Ku Cho , Chang-Ki Hong , Doo-Won Kwon
发明人： Chang-Sup Mun , Woo-Gwan Shim , Han-Ku Cho , Chang-Ki Hong , Doo-Won Kwon
IPC分类号： H01L21/302
CPC分类号： H01L21/02057 , H01L21/02082
摘要： A method for cleaning a substrate on which a silicon layer and a silicon germanium layer are formed and exposed, and method for fabricating a semiconductor device using the cleaning method are disclosed. The cleaning method comprises preparing a semiconductor substrate on which a silicon layer and a silicon germanium layer are formed and exposed; and performing a first cleaning sub-process that uses a first cleaning solution to remove a native oxide layer from the semiconductor substrate. The cleaning method further comprises performing a second cleaning sub-process on the semiconductor substrate after performing the first cleaning sub-process, wherein the second cleaning sub-process comprises using a second cleaning solution. In addition, the second cleaning solution comprises ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and deionized water (H2O), and the second cleaning solution comprises at least 200 times more deionized water (H2O) than ammonium hydroxide (NH4OH) by volume.
摘要翻译：公开了一种用于清洁其上形成和暴露硅层和硅锗层的衬底的方法，以及使用该清洁方法制造半导体器件的方法。该清洗方法包括：制备半导体衬底，在其上形成和暴露硅层和硅锗层; 以及执行使用第一清洁溶液以从半导体衬底去除自然氧化物层的第一清洁子过程。清洁方法还包括在执行第一清洁子过程之后在半导体衬底上执行第二清洁子处理，其中第二清洁子处理包括使用第二清洁溶液。此外，第二清洗溶液包括氢氧化铵（NH 4 OH），过氧化氢（H 2 O 2 O 2）和去离子水（ H 2 O），并且第二清洁溶液包含比氢氧化铵（NH 4 O 2）少至少200倍的去离子水（H 2 O 2 O） OH）。

8. 发明申请

US20080038732A1 Oligomer Probe Array and Method of Producing the Same 失效
标题翻译：低聚物探针阵列及其制备方法
公开(公告)号：US20080038732A1
公开(公告)日：2008-02-14
申请号：US11686506
申请日：2007-03-15
申请人： Jung-Hwan Hah , Sung-min Chi , Kyoung-seon Kim , Won-sun Kim , Han-ku Cho , Sang-jun Choi , Man-hyoung Ryoo
发明人： Jung-Hwan Hah , Sung-min Chi , Kyoung-seon Kim , Won-sun Kim , Han-ku Cho , Sang-jun Choi , Man-hyoung Ryoo
IPC分类号： C12Q1/68 , C07H21/00
CPC分类号： C12Q1/6834 , C12Q2563/155
摘要： An oligomer probe array having improved reaction yield is provided. The oligomer probe array includes a substrate, an immobilization layer on the substrate, a plurality of nano particles coupled with a surface of the immobilization layer, and a plurality of oligomer probes coupled with surfaces of the nano particles.
摘要翻译：提供了具有改善的反应产率的低聚物探针阵列。低聚物探针阵列包括基底，基底上的固定层，与固定层的表面耦合的多个纳米颗粒以及与纳米颗粒的表面耦合的多个低聚物探针。

9. 发明申请

US20070094635A1 Optical proximity correction system and methods thereof 有权
标题翻译：光学邻近校正系统及其方法
公开(公告)号：US20070094635A1
公开(公告)日：2007-04-26
申请号：US11585086
申请日：2006-10-24
申请人： Sung-Soo Suh , Young-Seog Kang , Han-Ku Cho , Sang-Gyun Woo
发明人： Sung-Soo Suh , Young-Seog Kang , Han-Ku Cho , Sang-Gyun Woo
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： An optical proximity correction (OPC) system and methods thereof are provided. The example OPC system may include an integrated circuit (IC) layout generation unit generating an IC layout, a database unit storing a first plurality of OPC models, each of the first plurality of OPC models associated with one of a plurality of target specific characteristics and a mask layout generation unit including a model selector selecting a second plurality of OPC models based on a comparison between the target specific characteristics associated with the plurality of OPC models and the generated IC layout, the mask layout generation unit generating a mask layout based on the IC layout and the selected second plurality of OPC models. A first example method may include storing a first plurality OPC models, each of the first plurality of OPC models associated with one of a plurality of target specific characteristics, generating an IC layout, selecting a second plurality of OPC models based on a comparison between the target specific characteristics associated with the first plurality of OPC models and the generated IC layout and generating a mask layout based on the generated IC layout and the selected second plurality of OPC models. A second example method may include applying a first OPC model to a first portion of a generated integrated circuit (IC) layout, applying a second OPC model to a second portion of the generated IC layout and generating a mask layout based on the generated IC layout after the application of the first and second OPC models.
摘要翻译：提供光学邻近校正（OPC）系统及其方法。示例性OPC系统可以包括产生IC布局的集成电路（IC）布局生成单元，存储第一多个OPC模型的数据库单元，与多个目标特定特征之一相关联的第一多个OPC模型中的每一个，以及掩模布局生成单元，其包括基于与所述多个OPC模型相关联的目标特定特性与所生成的IC布局之间的比较来选择第二多个OPC模型的模型选择器，所述掩模布局生成单元基于所述多个OPC模型生成掩模布局 IC布局和所选择的第二批OPC模型。第一示例性方法可以包括存储第一多个OPC模型，所述第一多个OPC模型中的每一个与多个目标特定特征中的一个相关联，生成IC布局，基于所述多个OPC模型之间的比较来选择第二多个OPC模型与第一多个OPC模型相关联的目标特定特征和所生成的IC布局，并且基于所生成的IC布局和所选择的第二多个OPC模型生成掩模布局。第二示例性方法可以包括将第一OPC模型应用于所生成的集成电路（IC）布局的第一部分，将第二OPC模型应用于所生成的IC布局的第二部分，并且基于所生成的IC布局生成掩模布局之后应用了第一个和第二个OPC模型。

10. 发明授权

US07205241B2 Method for manufacturing semiconductor device with contact body extended in direction of bit line 失效
标题翻译：具有沿位线方向延伸的接触体的半导体器件的制造方法
公开(公告)号：US07205241B2
公开(公告)日：2007-04-17
申请号：US10731931
申请日：2003-12-10
申请人： Chang-min Park , Jung-hyeon Lee , Han-ku Cho , Joon-soo Park
发明人： Chang-min Park , Jung-hyeon Lee , Han-ku Cho , Joon-soo Park
IPC分类号： H01L21/302
CPC分类号： H01L21/76897 , H01L21/76895 , H01L27/10855 , H01L27/10894 , H01L28/91 , Y10S438/942
摘要： Methods for manufacturing semiconductor devices with contact bodies extended in a direction of a bit line to increase the contact area between a contact body and a storage electrode is provided. In one aspect a method includes forming gate lines on a semiconductor substrate, forming a first insulating layer to cover the gate lines, forming first contact pads and second contact pads, which are electrically connected to the semiconductor substrate between the gate lines, by penetrating the first insulating layer. Further, a second insulating layer is formed to cover the first contact pads and the second contact pads, and bit lines are formed across over the gate lines and are electrically connected to the second contact pads by penetrating the second insulating layer. In addition, a third insulating layer is formed to cover the bit lines and is selectively etched to form a band-type opening that crosses the bit lines and exposes the first contact pads.
摘要翻译：提供了制造具有沿位线方向延伸的接触体以增加接触体与存储电极之间的接触面积的半导体器件的方法。在一个方面，一种方法包括在半导体衬底上形成栅极线，形成第一绝缘层以覆盖栅极线，形成第一接触焊盘和第二接触焊盘，这些接触焊盘和第二接触焊盘通过穿透栅极线与半导体衬底电连接第一绝缘层。此外，形成第二绝缘层以覆盖第一接触焊盘和第二接触焊盘，并且位线横跨栅极线形成，并且通过穿透第二绝缘层而电连接到第二接触焊盘。此外，形成第三绝缘层以覆盖位线，并且被选择性地蚀刻以形成穿过位线并暴露第一接触焊盘的带状开口。

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