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1. 发明授权

US09159767B2 Methods of manufacturing magnetoresistive random access memory devices 有权
标题翻译：制造磁阻随机存取存储器件的方法
公开(公告)号：US09159767B2
公开(公告)日：2015-10-13
申请号：US14182316
申请日：2014-02-18
申请人： Jong-Chul Park , Gwang-Hyun Baek , Hyung-Joon Kwon , In-Ho Kim , Chang-Woo Sun
发明人： Jong-Chul Park , Gwang-Hyun Baek , Hyung-Joon Kwon , In-Ho Kim , Chang-Woo Sun
IPC分类号： H01L43/12 , H01L27/22
CPC分类号： H01L27/228 , G11C11/161 , H01L43/12
摘要： In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed.
摘要翻译：在MRAM器件的方法中，第一和第二图案在第二方向上交替且重复地形成在衬底上。每个第一图案和每个第二图案沿垂直于第二方向的第一方向延伸。去除一些第二图案以形成沿第一方向延伸的第一开口。形成填充第一开口的源极线。在第一和第二图案和源极线上形成掩模。掩模包括沿第一方向的第二开口，每个开口沿第二方向延伸。由第二开口暴露的第二图案的部分被去除以形成第三开口。形成填充第三开口的第三图案。由第一图案和第三图案包围的第二图案被去除以形成第四开口。形成填充第四开口的接触塞。

2. 发明申请

US20140273287A1 METHOD OF MANUFACTURING THE SAME 有权
标题翻译：制造方法
公开(公告)号：US20140273287A1
公开(公告)日：2014-09-18
申请号：US14208912
申请日：2014-03-13
申请人： Jong-Chul PARK , Jae-Hun SEO , Byong-Jae BAE , Chang-Woo SUN
发明人： Jong-Chul PARK , Jae-Hun SEO , Byong-Jae BAE , Chang-Woo SUN
IPC分类号： H01L43/12
CPC分类号： H01L43/12 , G11C11/161 , H01L27/228
摘要： A method of manufacturing magnetoresistive random access memory (MRAM) device includes foaming first and second patterns on a substrate in an alternating and repeating arrangement, forming a first capping layer on top surfaces of the first and second patterns, and removing first portions of the first capping layer and a portion of the second patterns thereunder to form first openings exposing the substrate. The method further includes forming source lines filling lower portions of the first openings, respectively, forming second capping layer patterns filling upper portions of the first openings, respectively, and removing second portions of the first capping layer and a portion of the second patterns thereunder to form second openings exposing the substrate. Then, contact plugs and pad layers are integrally formed and sequentially stacked on the substrate to fill the second openings.
摘要翻译：一种制造磁阻随机存取存储器（MRAM）器件的方法包括以交替和重复布置在衬底上发泡第一和第二图案，在第一和第二图案的顶表面上形成第一覆盖层，以及去除第一和第二图案的第一部分盖层和其下的第二图案的一部分以形成暴露基板的第一开口。所述方法还包括分别形成填充所述第一开口的下部的源极线，分别形成填充所述第一开口的上部的第二封盖层图案，以及移除所述第一封盖层的第二部分及其下面的第二图案的一部分，形成露出衬底的第二开口。然后，将接触塞和垫层一体地形成并依次堆叠在基板上以填充第二开口。

3. 发明申请

US20140264672A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：磁性随机访问存储器件及其制造方法
公开(公告)号：US20140264672A1
公开(公告)日：2014-09-18
申请号：US14182316
申请日：2014-02-18
申请人： Jong-Chul Park , Gwang-Hyun Baek , Hyung-Joon Kwon , In-Ho Kim , Chang-Woo Sun
发明人： Jong-Chul Park , Gwang-Hyun Baek , Hyung-Joon Kwon , In-Ho Kim , Chang-Woo Sun
IPC分类号： H01L27/22 , H01L43/12
CPC分类号： H01L27/228 , G11C11/161 , H01L43/12
摘要： In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed.
摘要翻译：在MRAM器件的方法中，第一和第二图案在第二方向上交替且重复地形成在衬底上。每个第一图案和每个第二图案沿垂直于第二方向的第一方向延伸。去除一些第二图案以形成沿第一方向延伸的第一开口。形成填充第一开口的源极线。在第一和第二图案和源极线上形成掩模。掩模包括沿第一方向的第二开口，每个开口沿第二方向延伸。由第二开口暴露的第二图案的部分被去除以形成第三开口。形成填充第三开口的第三图案。由第一图案和第三图案包围的第二图案被去除以形成第四开口。形成填充第四开口的接触塞。

4. 发明申请

US20140024189A1 Vertical Memory Devices and Methods of Manufacturing the Same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20140024189A1
公开(公告)日：2014-01-23
申请号：US13943911
申请日：2013-07-17
申请人： Bi-O Kim , Toshiro Nakanishi , Jin-Tae Noh , Chang-Woo Sun , Seung-Hyun Lim , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Bi-O Kim , Toshiro Nakanishi , Jin-Tae Noh , Chang-Woo Sun , Seung-Hyun Lim , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L29/66
CPC分类号： H01L29/66666 , H01L21/8239 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.
摘要翻译：提供制造垂直存储器件的方法包括在衬底上形成多个交替绝缘层和牺牲层; 图案化和蚀刻所述多个绝缘层和牺牲层以限定暴露所述衬底的表面的至少一部分的开口; 在开口的侧壁上形成电荷捕获图案和隧道绝缘图案; 在开口的侧壁上的隧道绝缘层上形成沟道层，沟道层包括N型杂质掺杂多晶硅; 在开口中的沟道层上形成掩埋绝缘图案; 以及在沟道层的一个侧壁的电荷捕获图案上形成阻挡电介质层和控制栅极。

5. 发明申请

US20130270631A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20130270631A1
公开(公告)日：2013-10-17
申请号：US13796394
申请日：2013-03-12
申请人： Bi-o KIM , Jin-tae NOH , Chang-woo SUN , Jae-young AHN , Seung-hyun LIM , Ki-hyun HWANG
发明人： Bi-o KIM , Jin-tae NOH , Chang-woo SUN , Jae-young AHN , Seung-hyun LIM , Ki-hyun HWANG
IPC分类号： H01L29/78
CPC分类号： H01L29/66666 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/42332 , H01L29/7827
摘要： A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.

6. 发明授权

US09064895B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09064895B2
公开(公告)日：2015-06-23
申请号：US13943911
申请日：2013-07-17
申请人： Bi-O Kim , Toshiro Nakanishi , Jin-Tae Noh , Chang-Woo Sun , Seung-Hyun Lim , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Bi-O Kim , Toshiro Nakanishi , Jin-Tae Noh , Chang-Woo Sun , Seung-Hyun Lim , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L27/115 , H01L29/66 , H01L21/8239 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66666 , H01L21/8239 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.
摘要翻译：提供制造垂直存储器件的方法包括在衬底上形成多个交替绝缘层和牺牲层; 图案化和蚀刻所述多个绝缘层和牺牲层以限定暴露所述衬底的表面的至少一部分的开口; 在开口的侧壁上形成电荷捕获图案和隧道绝缘图案; 在开口的侧壁上的隧道绝缘层上形成沟道层，沟道层包括N型杂质掺杂多晶硅; 在开口中的沟道层上形成掩埋绝缘图案; 以及在沟道层的一个侧壁的电荷捕获图案上形成阻挡电介质层和控制栅极。

7. 发明申请

US20120284772A1 DATA STORAGE DEVICE AUTHENTICATION APPARATUS AND DATA STORAGE DEVICE INCLUDING AUTHENTICATION APPARATUS CONNECTOR 审中-公开
标题翻译：数据存储设备认证设备和数据存储设备，包括认证设备连接器
公开(公告)号：US20120284772A1
公开(公告)日：2012-11-08
申请号：US13457649
申请日：2012-04-27
申请人： Moon-Sang Kwon , Bo-Gyeong Kang , Jung-Wan Ko , Chang-Woo Sun , Byung-Rae Lee
发明人： Moon-Sang Kwon , Bo-Gyeong Kang , Jung-Wan Ko , Chang-Woo Sun , Byung-Rae Lee
IPC分类号： G06F21/00
CPC分类号： G06F21/44 , G11C16/22
摘要： An authentication apparatus includes a data storage unit for storing authentication apparatus identification information, an interface unit for connecting to a host device through a first interface, and an authentication processor that executes an authentication process using the authentication apparatus identification information stored in the data storage unit. The authentication processor executes the authentication process upon receipt of an authentication request signal from the host device through the interface unit, and outputs an authentication response signal including data indicative of a result of the authentication process to the host device via the interface unit. The authentication request signal is for requesting authentication of a data storage device connected to the host device through a second interface.
摘要翻译：认证装置包括用于存储认证装置识别信息的数据存储单元，用于通过第一接口连接到主机设备的接口单元和使用存储在数据存储单元中的认证装置识别信息执行认证处理的认证处理器。认证处理器在通过接口单元从主机设备接收到认证请求信号时执行认证处理，并且经由接口单元向主机设备输出包括表示认证处理结果的数据的认证响应信号。认证请求信号用于通过第二接口请求与主机设备连接的数据存储设备的认证。

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