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1. 发明授权

US09064895B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09064895B2
公开(公告)日：2015-06-23
申请号：US13943911
申请日：2013-07-17
申请人： Bi-O Kim , Toshiro Nakanishi , Jin-Tae Noh , Chang-Woo Sun , Seung-Hyun Lim , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Bi-O Kim , Toshiro Nakanishi , Jin-Tae Noh , Chang-Woo Sun , Seung-Hyun Lim , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L27/115 , H01L29/66 , H01L21/8239 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66666 , H01L21/8239 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.
摘要翻译：提供制造垂直存储器件的方法包括在衬底上形成多个交替绝缘层和牺牲层; 图案化和蚀刻所述多个绝缘层和牺牲层以限定暴露所述衬底的表面的至少一部分的开口; 在开口的侧壁上形成电荷捕获图案和隧道绝缘图案; 在开口的侧壁上的隧道绝缘层上形成沟道层，沟道层包括N型杂质掺杂多晶硅; 在开口中的沟道层上形成掩埋绝缘图案; 以及在沟道层的一个侧壁的电荷捕获图案上形成阻挡电介质层和控制栅极。

2. 发明申请

US20140024189A1 Vertical Memory Devices and Methods of Manufacturing the Same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20140024189A1
公开(公告)日：2014-01-23
申请号：US13943911
申请日：2013-07-17
申请人： Bi-O Kim , Toshiro Nakanishi , Jin-Tae Noh , Chang-Woo Sun , Seung-Hyun Lim , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Bi-O Kim , Toshiro Nakanishi , Jin-Tae Noh , Chang-Woo Sun , Seung-Hyun Lim , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L29/66
CPC分类号： H01L29/66666 , H01L21/8239 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.
摘要翻译：提供制造垂直存储器件的方法包括在衬底上形成多个交替绝缘层和牺牲层; 图案化和蚀刻所述多个绝缘层和牺牲层以限定暴露所述衬底的表面的至少一部分的开口; 在开口的侧壁上形成电荷捕获图案和隧道绝缘图案; 在开口的侧壁上的隧道绝缘层上形成沟道层，沟道层包括N型杂质掺杂多晶硅; 在开口中的沟道层上形成掩埋绝缘图案; 以及在沟道层的一个侧壁的电荷捕获图案上形成阻挡电介质层和控制栅极。

3. 发明申请

US20070066083A1 Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same 有权
标题翻译：通过原子层沉积工艺形成富硅纳米晶体结构的方法和使用其制造非易失性半导体器件的方法
公开(公告)号：US20070066083A1
公开(公告)日：2007-03-22
申请号：US11494451
申请日：2006-07-28
申请人： Sang-Ryol Yang , Kyong-Hee Joo , In-Seok Yeo , Ki-Hyun Hwang , Seung-Hyun Lim
发明人： Sang-Ryol Yang , Kyong-Hee Joo , In-Seok Yeo , Ki-Hyun Hwang , Seung-Hyun Lim
IPC分类号： H01L21/31 , H01L21/469 , H01L21/4763
CPC分类号： H01L21/02164 , B82Y10/00 , C23C16/308 , C23C16/401 , C23C16/45529 , H01L21/0214 , H01L21/02211 , H01L21/0228 , H01L21/02337 , H01L21/28273 , H01L21/3141 , H01L21/32055 , H01L29/42328 , Y10S438/962
摘要： In a method of forming a silicon-rich nanocrystalline structure by an ALD process, a first gas including a first silicon compound is provided onto an object to form a silicon-rich chemisorption layer on the object. A second gas including oxygen is provided onto the silicon-rich chemisorption layer to form a silicon-rich insulation layer on the object. A third gas including a second silicon compound is provided onto the silicon-rich insulation layer to form a silicon nanocrystalline layer on the silicon-rich insulation layer. The first gas, the second gas and the third gas may be repeatedly provided to alternately form the silicon-rich nanocrystalline structure having a plurality of silicon-rich insulation layers and a plurality of silicon nanocrystalline layers on the object.
摘要翻译：在通过ALD工艺形成富含硅的纳米晶体结构的方法中，将包含第一硅化合物的第一气体提供到物体上以在物体上形成富含硅的化学吸附层。在富含硅的化学吸附层上提供包含氧的第二气体，以在物体上形成富含硅的绝缘层。在富硅绝缘层上提供包括第二硅化合物的第三气体，以在富硅绝缘层上形成硅纳米晶层。可以重复地提供第一气体，第二气体和第三气体以交替地形成在物体上具有多个富硅绝缘层和多个硅纳米晶层的富含硅的纳米晶体结构。

4. 发明授权

US07419888B2 Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same 有权
标题翻译：通过原子层沉积工艺形成富硅纳米晶体结构的方法和使用其制造非易失性半导体器件的方法
公开(公告)号：US07419888B2
公开(公告)日：2008-09-02
申请号：US11494451
申请日：2006-07-28
申请人： Sang-Ryol Yang , Kyong-Hee Joo , In-Seok Yeo , Ki-Hyun Hwang , Seung-Hyun Lim
发明人： Sang-Ryol Yang , Kyong-Hee Joo , In-Seok Yeo , Ki-Hyun Hwang , Seung-Hyun Lim
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02164 , B82Y10/00 , C23C16/308 , C23C16/401 , C23C16/45529 , H01L21/0214 , H01L21/02211 , H01L21/0228 , H01L21/02337 , H01L21/28273 , H01L21/3141 , H01L21/32055 , H01L29/42328 , Y10S438/962
摘要： In a method of forming a silicon-rich nanocrystalline structure by an ALD process, a first gas including a first silicon compound is provided onto an object to form a silicon-rich chemisorption layer on the object. A second gas including oxygen is provided onto the silicon-rich chemisorption layer to form a silicon-rich insulation layer on the object. A third gas including a second silicon compound is provided onto the silicon-rich insulation layer to form a silicon nanocrystalline layer on the silicon-rich insulation layer. The first gas, the second gas and the third gas may be repeatedly provided to alternately form the silicon-rich nanocrystalline structure having a plurality of silicon-rich insulation layers and a plurality of silicon nanocrystalline layers on the object.
摘要翻译：在通过ALD工艺形成富含硅的纳米晶体结构的方法中，将包含第一硅化合物的第一气体提供到物体上以在物体上形成富含硅的化学吸附层。在富含硅的化学吸附层上提供包含氧的第二气体，以在物体上形成富含硅的绝缘层。在富硅绝缘层上提供包括第二硅化合物的第三气体，以在富硅绝缘层上形成硅纳米晶层。可以重复地提供第一气体，第二气体和第三气体以交替地形成在物体上具有多个富硅绝缘层和多个硅纳米晶层的富含硅的纳米晶体结构。

5. 发明申请

US20120098990A1 ANALOG-TO-DIGITAL CONVERTER AND IMAGE SENSOR INCLUDING THE SAME 有权
标题翻译：模拟数字转换器和图像传感器，包括它们
公开(公告)号：US20120098990A1
公开(公告)日：2012-04-26
申请号：US13240670
申请日：2011-09-22
申请人： Wun-Ki JUNG , Seung-Hyun Lim , Dong-Hun Lee , Kwi-Sung Yoo , Min-Ho Kwon , Chi-Ho Hwang
发明人： Wun-Ki JUNG , Seung-Hyun Lim , Dong-Hun Lee , Kwi-Sung Yoo , Min-Ho Kwon , Chi-Ho Hwang
IPC分类号： H04N5/228 , H03M1/12
CPC分类号： H04N5/378 , H03M1/162 , H03M1/56 , H04N5/3575 , H04N5/374
摘要： An analog-to-digital converter includes a comparison signal generation unit and a control unit. The comparison signal generation unit determines a logic level of a comparison signal by comparing an input signal with a selected reference signal based on a switch control signal in a first comparison mode, and by comparing a difference voltage with a ramp signal based on the switch control signal in a second comparison mode. The difference voltage is generated based on the input signal and the selected reference signal such that a level of the difference voltage is lower than a fine voltage level corresponding to a voltage level of the selected reference signal in the second comparison mode. The control unit generates the switch control signal based on the comparison signal and a mode selection signal.
摘要翻译：模数转换器包括比较信号生成单元和控制单元。比较信号生成单元通过在第一比较模式中基于开关控制信号比较输入信号与所选择的参考信号，并且通过基于开关控制将差分电压与斜坡信号进行比较来确定比较信号的逻辑电平信号在第二比较模式。基于输入信号和所选择的参考信号产生差分电压，使得差分电压的电平低于与第二比较模式中所选参考信号的电压电平相对应的精细电压电平。控制单元基于比较信号和模式选择信号产生开关控制信号。

6. 发明申请

US20080246078A1 Charge trap flash memory device and memory card and system including the same 有权
标题翻译：充电陷阱闪存设备和存储卡及系统包括相同
公开(公告)号：US20080246078A1
公开(公告)日：2008-10-09
申请号：US12080315
申请日：2008-04-02
申请人： Zong-liang Huo , In-seok Yeo , Seung-Hyun Lim , Kyong-hee Joo , Jun-kyu Yang
发明人： Zong-liang Huo , In-seok Yeo , Seung-Hyun Lim , Kyong-hee Joo , Jun-kyu Yang
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332 , H01L29/7881
摘要： A charge trap flash memory device and method of making same are provided. The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.
摘要翻译：提供了一种电荷阱闪存器件及其制造方法。该器件包括：隧道绝缘层，电荷陷阱层; 阻挡绝缘层; 以及依次形成在基板上的栅电极。电荷陷阱层包括：多个陷阱层，包括具有第一带隙能级的第一材料; 间隔开的纳米点，每个纳米点至少部分地被至少一个捕获层包围，其中该纳米点包括具有低于第一带隙能级的第二带隙能级的第二材料; 以及中间阻挡层，其包括形成在至少两个捕获层之间的具有高于第一带隙能级的第三带隙能级的第三材料。这种结构防止电荷陷阱层的电荷损失并且改善电荷存储容量。

7. 发明授权

US08659339B2 Offset canceling circuit, sampling circuit and image sensor 有权
标题翻译：偏移消除电路，采样电路和图像传感器
公开(公告)号：US08659339B2
公开(公告)日：2014-02-25
申请号：US13272723
申请日：2011-10-13
申请人： Wun-Ki Jung , Kwi-Sung Yoo , Min-Ho Kwon , Jae-Hong Kim , Seung-Hyun Lim , Yu-Jin Park
发明人： Wun-Ki Jung , Kwi-Sung Yoo , Min-Ho Kwon , Jae-Hong Kim , Seung-Hyun Lim , Yu-Jin Park
IPC分类号： H03L5/00
CPC分类号： H04N5/363 , H04N5/3575 , H04N5/378
摘要： An offset canceling circuit stores charge corresponding to a voltage difference between a reset voltage received from a unit pixel and a reference voltage, thereby canceling an offset of the unit pixel.
摘要翻译：偏移消除电路存储对应于从单位像素接收的复位电压与参考电压之间的电压差的电荷，从而消除单位像素的偏移。

8. 发明申请

US20070123019A1 METHODS OF FORMING CARBON NANOTUBES IN A WIRING PATTERN AND RELATED DEVICES 审中-公开
标题翻译：在配线图案和相关设备中形成碳纳米管的方法
公开(公告)号：US20070123019A1
公开(公告)日：2007-05-31
申请号：US11470369
申请日：2006-09-06
申请人： Seung-Hyun Lim , Sun-Woo Lee , In-Seok Yeo
发明人： Seung-Hyun Lim , Sun-Woo Lee , In-Seok Yeo
IPC分类号： H01L21/44
CPC分类号： H01L21/76802 , H01L21/76876 , H01L21/76879 , H01L2221/1094
摘要： A method of forming a carbon nanotube includes forming a cavity between a substrate and a first layer on the substrate. The cavity extends in a wiring pattern and includes a metal catalyst pattern in the cavity. The carbon nanotube is formed from the metal catalyst pattern and extends inside the cavity along the wiring pattern. Related methods and devices are also discussed.
摘要翻译：形成碳纳米管的方法包括在基板和基板上的第一层之间形成空腔。空腔以布线图案延伸，并且在空腔中包括金属催化剂图案。碳纳米管由金属催化剂图案形成，并沿着布线图案在腔内延伸。还讨论了相关的方法和设备。

9. 发明授权

US08547461B2 Analog-to-digital converter having a comparison signal generation unit and image sensor including the same 有权
标题翻译：具有比较信号生成单元和包含该比较信号生成单元的图像传感器的模数转换器
公开(公告)号：US08547461B2
公开(公告)日：2013-10-01
申请号：US13240670
申请日：2011-09-22
申请人： Wun-Ki Jung , Seung-Hyun Lim , Dong-Hun Lee , Kwi-Sung Yoo , Min-Ho Kwon , Chi-Ho Hwang
发明人： Wun-Ki Jung , Seung-Hyun Lim , Dong-Hun Lee , Kwi-Sung Yoo , Min-Ho Kwon , Chi-Ho Hwang
IPC分类号： H04N3/14 , H03M1/12
CPC分类号： H04N5/378 , H03M1/162 , H03M1/56 , H04N5/3575 , H04N5/374
摘要： An analog-to-digital converter includes a comparison signal generation unit and a control unit. The comparison signal generation unit determines a logic level of a comparison signal by comparing an input signal with a selected reference signal based on a switch control signal in a first comparison mode, and by comparing a difference voltage with a ramp signal based on the switch control signal in a second comparison mode. The difference voltage is generated based on the input signal and the selected reference signal such that a level of the difference voltage is lower than a fine voltage level corresponding to a voltage level of the selected reference signal in the second comparison mode. The control unit generates the switch control signal based on the comparison signal and a mode selection signal.
摘要翻译：模数转换器包括比较信号生成单元和控制单元。比较信号生成单元通过在第一比较模式中基于开关控制信号比较输入信号与所选择的参考信号，并且通过基于开关控制将差分电压与斜坡信号进行比较来确定比较信号的逻辑电平信号在第二比较模式。基于输入信号和所选择的参考信号产生差分电压，使得差分电压的电平低于与第二比较模式中所选参考信号的电压电平相对应的精细电压电平。控制单元基于比较信号和模式选择信号产生开关控制信号。

10. 发明申请

US20110198685A1 Non-Volatile Memory Devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US20110198685A1
公开(公告)日：2011-08-18
申请号：US13095408
申请日：2011-04-27
申请人： Hyun-Suk Kim , Sun-II Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
发明人： Hyun-Suk Kim , Sun-II Shim , Chang-Seok Kang , Won-Cheol Jeong , Jung-Dal Choi , Jae-Kwan Park , Seung-Hyun Lim , Sun-Jung Kim
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792
摘要： Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.
摘要翻译：提供了非易失性存储器件，其包括在衬底上的控制栅电极; 在控制栅电极和衬底之间的电荷存储绝缘层; 在电荷存储绝缘层和衬底之间的隧道绝缘层; 电荷存储绝缘层和控制栅电极之间的阻挡绝缘层; 以及隧道绝缘层和阻挡绝缘层之间的材料层，材料层具有构成势阱底部的能级。

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