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1. 发明申请

US20090164678A1 PERIPHERAL DEVICE COMPLYING WITH SDIO STANDARD AND METHOD FOR MANAGING SDIO COMMAND 审中-公开
标题翻译：符合SDIO标准的外围设备和管理SDIO命令的方法
公开(公告)号：US20090164678A1
公开(公告)日：2009-06-25
申请号：US12246853
申请日：2008-10-07
申请人： Chao-Yu HU
发明人： Chao-Yu HU
IPC分类号： G06F13/42
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0673 , G06F13/42 , G06F2003/0691
摘要： The invention provides a method of managing SDIO commands. Firstly, before a first packet complying with a first SDIO data format is transmitted, an operation request is converted into a converted command. The operation request is originally set to be converted into a command complying with a SDIO command format. Then, the fist packet and the converted command are combined to generate a first combined packet. Afterward, the first combined packet is transmitted. After the first combined packet is received, the first combined packet is parsed to obtain the converted command. Finally, a processing procedure is performed according to the converted command.
摘要翻译：本发明提供一种管理SDIO命令的方法。首先，在发送符合第一SDIO数据格式的第一分组之前，将操作请求转换为转换的命令。操作请求最初设置为转换成符合SDIO命令格式的命令。然后，组合第一分组和转换的命令以生成第一组合分组。之后，发送第一个组合数据包。在接收到第一组合分组之后，解析第一组合分组以获得转换的命令。最后，根据转换的命令执行处理过程。

2. 发明申请

US20090172202A1 Method for Receiving Data over an SDIO Interface and Device Using the Same 有权
标题翻译：通过SDIO接口接收数据的方法及其使用方法
公开(公告)号：US20090172202A1
公开(公告)日：2009-07-02
申请号：US12264257
申请日：2008-11-04
申请人： Check-Yan Goh , Chao-Yu Hu
发明人： Check-Yan Goh , Chao-Yu Hu
IPC分类号： G06F3/00
CPC分类号： G06F21/85
摘要： A method for receiving data with a secure digital input/output (SDIO) interface, which is utilized for providing a data transmission connection between a master device and a slave device, starts with receiving a first packet of the data from the slave device. The first packet is transferred with a plurality of data blocks. A first data block of the plurality of data blocks has reception information of a second packet. The method then generates a control signal to receive the second packet from the slave device according to the reception information of the second packet, which is a next packet of the first packet in the data.
摘要翻译：用于在主设备和从设备之间提供数据传输连接的安全数字输入/输出（SDIO）接口接收数据的方法开始于从从设备接收数据的第一分组。第一个分组被传送与多个数据块。多个数据块的第一数据块具有第二分组的接收信息。该方法然后根据作为数据中的第一分组的下一个分组的第二分组的接收信息产生控制信号以从从设备接收第二分组。

3. 发明授权

US07840722B2 Method for receiving data over an SDIO interface and device using the same 有权
标题翻译：通过SDIO接口接收数据的方法和使用该数据的设备
公开(公告)号：US07840722B2
公开(公告)日：2010-11-23
申请号：US12264257
申请日：2008-11-04
申请人： Cheok-Yan Goh , Chao-Yu Hu
发明人： Cheok-Yan Goh , Chao-Yu Hu
IPC分类号： G06F13/14 , G06F13/00
CPC分类号： G06F21/85
摘要： A method for receiving data with a secure digital input/output (SDIO) interface, which is utilized for providing a data transmission connection between a master device and a slave device, starts with receiving a first packet of the data from the slave device. The first packet is transferred with a plurality of data blocks. A first data block of the plurality of data blocks has reception information of a second packet. The method then generates a control signal to receive the second packet from the slave device according to the reception information of the second packet, which is a next packet of the first packet in the data.
摘要翻译：用于在主设备和从设备之间提供数据传输连接的安全数字输入/输出（SDIO）接口接收数据的方法开始于从从设备接收数据的第一分组。第一个分组被传送与多个数据块。多个数据块的第一数据块具有第二分组的接收信息。该方法然后根据作为数据中的第一分组的下一个分组的第二分组的接收信息产生控制信号以从从设备接收第二分组。

4. 发明授权

US06959066B2 Device for programmable frequency divider 失效
标题翻译：可编程分频器的设备
公开(公告)号：US06959066B2
公开(公告)日：2005-10-25
申请号：US10392910
申请日：2003-03-21
申请人： Jung-Chih Wang , Chao-Yu Hu
发明人： Jung-Chih Wang , Chao-Yu Hu
IPC分类号： H03K23/66 , H03K21/00
CPC分类号： H03K23/662
摘要： The present invention relates to a programmable frequency divider having one n-bit adder and one n-bit D Flip Flop. These are used to transform the import clock to the target clock. The adder takes one adjustment parameter and one return signal as a basis to create the first output signal, with the possibility to program the adjustment parameter. The D Flip Flop and the adder create a cycle, which is used to receive the first output signal and its import clock to create the second output signal. The second output signal is separated into a return signal and the target signal. The D Flip Flop sends the return signal back to the adder, which will make addition calculations under the adjustment parameter, finally giving out the target clock with the target signal as a calculation basis.
摘要翻译：本发明涉及具有一个n位加法器和一个n位D触发器的可编程分频器。这些用于将导入时钟转换为目标时钟。加法器采用一个调整参数和一个返回信号作为创建第一个输出信号的基础，可编程调整参数。 D触发器和加法器产生一个周期，用于接收第一个输出信号及其导入时钟以产生第二个输出信号。第二输出信号被分离为返回信号和目标信号。 D触发器将返回信号发送回加法器，这将在调整参数下进行加法运算，最终以目标信号作为计算依据给出目标时钟。

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