专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11777509B2 Radar system and related method of scanning remote objects 有权
公开(公告)号：US11777509B2
公开(公告)日：2023-10-03
申请号：US17871433
申请日：2022-07-22
申请人： TRON FUTURE TECH INC.
发明人： Yu-Jiu Wang , Bor-Ching Su
IPC分类号： H03L7/18 , H03K23/66 , H03L7/24 , H03L7/00 , H04L7/00 , H04W56/00 , H03K21/00 , G01S7/02 , G01S7/295 , G01S13/34 , H04B7/06
CPC分类号： H03L7/18 , H03K21/00 , H03K23/662 , H03K23/667 , H03L7/00 , H03L7/24 , H04L7/0008 , H04L7/0037 , H04W56/004 , G01S7/021 , G01S7/295 , G01S13/341 , H04B7/0617
摘要： A radar system includes: a plurality of first receiving devices for generating a plurality of first digital signals according to a plurality of first incoming signals, respectively; and a plurality of second receiving devices for generating a plurality of second digital signals according to a plurality of second incoming signals, respectively. A processing device is arranged to perform a first beamforming operation to generate a plurality of first beamforming signals according to the plurality of first digital signals and a first gain matrix, and to perform a second beamforming operation to generate a plurality of second beamforming signals according to the plurality of second digital signals and a second gain matrix; and to determine an altitude angle of a first object and a second object, and to determine a first azimuth angle of the first object and a second azimuth angle of the second object.

2. 发明授权

US10530368B1 Load compensation to reduce deterministic jitter in clock applications 有权
公开(公告)号：US10530368B1
公开(公告)日：2020-01-07
申请号：US16191755
申请日：2018-11-15
申请人： Silicon Laboratories Inc.
发明人： Aaron J. Caffee , Brian G. Drost
IPC分类号： H03K23/66 , H03K21/02
摘要： A clock circuit includes a circuit configured to use a regulated voltage on a regulated voltage node to provide a frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency. The clock circuit includes an auxiliary loading circuit coupled to the regulated voltage node and configured to selectively provide load compensation for a load difference of the circuit. The load difference is a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency. The circuit may include a frequency divider circuit configured to use the regulated voltage on the regulated voltage node to generate the frequency modulated clock signal by frequency dividing an input clock signal according to a divide value vacillating between a first divide value and a second divide value.

3. 发明授权

US10348275B2 Frequency-divider circuitry 有权
公开(公告)号：US10348275B2
公开(公告)日：2019-07-09
申请号：US16039760
申请日：2018-07-19
申请人： Cirrus Logic International Semiconductor Ltd.
发明人： Dario San Martin Molina , Gordon James Bates
IPC分类号： H03K23/00 , H03K3/03 , H03K23/66 , G06F1/04 , H03L7/197 , H03L7/099 , H03K23/54
摘要： There is disclosed configurable frequency-divider circuitry for generating a target signal of a frequency Fr/Di based on a reference signal of a frequency Fr, where Di is an integer divider ratio, the frequency-divider circuitry comprising: N divider stages organised into a ring, each stage configured to receive an input signal and generate an output signal, with the output signal of each successive stage in the ring being the input signal of the next stage in the ring, wherein: the ring of stages is controlled by the reference signal so that the output signals are governed by the reference signal; the target signal is one of the output signals or a signal derived therefrom; and at least one of the stages is a configurable stage, whose mode of operation is configurable based on a configuration signal to configure the value of Di.

4. 发明授权

US10056890B2 Digital controlled oscillator based clock generator for multi-channel design 有权
公开(公告)号：US10056890B2
公开(公告)日：2018-08-21
申请号：US15192970
申请日：2016-06-24
申请人： Exar Corporation
发明人： Omeshwar Lawange
IPC分类号： H03K21/00 , H03K5/14 , H03K21/10 , H03K3/037 , H03K23/66 , H03K23/68 , H03K5/00
CPC分类号： H03K5/14 , H03K3/037 , H03K21/10 , H03K23/66 , H03K23/68 , H03K2005/00058
摘要： A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay line includes, in part, a chain of delay elements configured to generate a multitude of delays of the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count.

5. 发明申请

US20170366193A1 PROGRAMMABLE FREQUENCY DIVIDER, PLL SYNTHESIZER AND RADAR DEVICE 审中-公开
公开(公告)号：US20170366193A1
公开(公告)日：2017-12-21
申请号：US15609925
申请日：2017-05-31
申请人： FUJITSU LIMITED
发明人： Hiroshi Matsumura
IPC分类号： H03L7/199 , H03K23/66 , G01S7/02
CPC分类号： H03L7/199 , G01S7/02 , G01S7/03 , G01S7/35 , H03K23/667 , H03L7/1974
摘要： A programmable frequency divider includes a modulus frequency divider, a pulse counter, and a swallow counter. The pulse counter is configured to count an output signal from the modulus frequency divider, and output a frequency division signal, and the swallow counter is configured to count the output signal from the modulus frequency divider and perform resetting on the basis of the frequency division signal from the pulse counter, the programmable frequency divider being configured to control the modulus frequency divider on the basis of a signal from the swallow counter. The programmable frequency divider includes a control signal delay circuit, disposed between an output terminal of the swallow counter and a control terminal of the modulus frequency divider, configured to delay a signal from the swallow counter, and generate a control signal for controlling the modulus frequency divider.

6. 发明授权

US09553595B2 Clock operation method and circuit 有权
标题翻译：时钟操作方法和电路
公开(公告)号：US09553595B2
公开(公告)日：2017-01-24
申请号：US14614783
申请日：2015-02-05
申请人： MegaChips Corporation
发明人： Tomohiro Wanibuchi
IPC分类号： G06F1/10 , H03L7/18 , H03K5/153 , G06F1/08 , G06F1/12 , H03K23/66
CPC分类号： H03L7/18 , G06F1/08 , G06F1/10 , G06F1/12 , H03K5/153 , H03K23/66
摘要： In a clock generating circuit, a variable frequency division circuit generates a variable divided clock by dividing a source clock in accordance with a division ratio setting signal. A first clock synchronization circuit generates a first delayed clock that is delayed by a maximum number of clocks from the variable divided clock in synchronization with the source clock and supplies the first delayed clock to a control circuit. One or more second clock synchronization circuits generate one or more second delayed clocks, each of which is delayed by the maximum number of clocks from the variable divided clock in synchronization with the source clock, and supply each of the one or more second delayed clocks to each of one or more functional modules.
摘要翻译：在时钟发生电路中，可变分频电路通过根据分频比设置信号划分源时钟来产生可变分频时钟。第一时钟同步电路产生与源时钟同步地从可变分频时钟延迟最大数量的时钟的第一延迟时钟，并将第一延迟时钟提供给控制电路。一个或多个第二时钟同步电路产生一个或多个第二延迟时钟，每个第二延迟时钟与源时钟同步地从可变分频时钟延迟最大时钟数，并将一个或多个第二延迟时钟中的每一个提供给每个一个或多个功能模块。

7. 发明授权

US09344093B2 Counter 有权
标题翻译：计数器
公开(公告)号：US09344093B2
公开(公告)日：2016-05-17
申请号：US14474314
申请日：2014-09-02
申请人： Nuvoton Technology Corporation
发明人： Tsung-Hsien Hsieh
IPC分类号： H03K21/00 , H03K21/38 , H03K21/40 , H03K23/66
CPC分类号： H03K21/38 , H03K21/00 , H03K21/40 , H03K23/665
摘要： A counter including a state determination unit and a counter reset unit is provided. The state determination unit is for receiving a current count value to calculate a next count value. The counter reset unit compares a reset counter value and a delay cycle value to determine using a first comparator or a second comparator, and compares the reset counter value and the current count value to output a counter reset signal to the state determination unit to reset the current count value, wherein a bit number of the first comparator is smaller than a bit number of the second comparator.
摘要翻译：提供了包括状态确定单元和计数器复位单元的计数器。状态确定单元用于接收当前计数值以计算下一个计数值。计数器复位单元将复位计数器值和延迟周期值进行比较，以确定使用第一比较器或第二比较器，并将复位计数器值和当前计数值进行比较，以将计数器复位信号输出到状态判定单元，当前计数值，其中第一比较器的位数小于第二比较器的位数。

8. 发明授权

US09325541B2 Modular frequency divider with switch configuration to reduce parasitic capacitance 有权
标题翻译：具有开关配置的模块化分频器，以减少寄生电容
公开(公告)号：US09325541B2
公开(公告)日：2016-04-26
申请号：US14279780
申请日：2014-05-16
申请人： Marvell World Trade LTD.
发明人： Alberto Pirola , Danilo Gerna
IPC分类号： H04B1/04 , H04L25/08 , H04L25/03 , H03B19/00 , H03K23/66 , H03K21/10 , H04W52/36
CPC分类号： H04L25/08 , H03B19/00 , H03K21/10 , H03K23/667 , H04L25/03828 , H04W52/367
摘要： A system comprising a first frequency divider to divide an input frequency of an input signal to generate a first signal having a first frequency and a first phase. Each of a plurality of second frequency dividers divides the input frequency of the input signal to generate a second signal having the first frequency and a second phase. A first switch includes a first end connected to a first node of the first frequency divider, and a second end connected to a second node of a first one of the plurality of second frequency dividers. A plurality of second switches include first ends connected to the second end of the first switch, and second ends respectively connected to the second nodes of the plurality of second frequency dividers other than the first one of the plurality of second frequency dividers.
摘要翻译：一种系统，包括：第一分频器，用于对输入信号的输入频率进行分频，以产生具有第一频率和第一相位的第一信号。多个第二分频器中的每一个分频器将输入信号的输入频率除以产生具有第一频率和第二相位的第二信号。第一开关包括连接到第一分频器的第一节点的第一端和连接到多个第二分频器中的第一分频器的第二节点的第二端。多个第二开关包括连接到第一开关的第二端的第一端和分别连接到多个第二分频器中除第一分频器中的第一分频器之外的多个第二分频器的第二节点的第二端。

9. 发明授权

US09258506B2 Counter circuit, analog-to-digital converter, and image sensor including the same and method of correlated double sampling 有权
标题翻译：计数器电路，模数转换器和图像传感器包括相同的方法和相关的双重采样方法
公开(公告)号：US09258506B2
公开(公告)日：2016-02-09
申请号：US14335309
申请日：2014-07-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ji-Hun Shin , Chang-Eun Kang , Won-Ho Choi , Dong-Hun Lee
IPC分类号： H04N5/335 , H04N5/378 , H03K21/38 , H03K23/66 , H03M1/14 , H03M1/12 , H03M1/56 , H04N5/357 , H04N5/369 , H04N5/3745 , H04N13/02
CPC分类号： H04N5/378 , H03K21/38 , H03K23/667 , H03M1/123 , H03M1/14 , H03M1/56 , H04N5/3575 , H04N5/3696 , H04N5/3745 , H04N13/243 , H04N13/254 , H04N13/271 , H04N2213/001
摘要： A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N−M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.
摘要翻译：计数器电路包括第一计数器和第二计数器。第一计数器被配置为响应于基于第一比较的第一计数使能信号来计数与第一频率切换的第一计数器时钟信号，以产生N位计数器输出信号的上（N-M）位信号信号在粗计数间隔期间。 N和M是自然数，N大于M，M大于或等于3.第二计数器被配置为对第二计数器时钟信号进行计数，第二计数器时钟信号与第二频率相交换，第二频率高于第一频率以产生响应于基于第一比较信号的第二计数使能信号和在粗计数间隔之后的精细计数间隔期间的第二比较信号，N比特计数器输出信号的较低M比特信号。

10. 发明授权

US09118333B1 Self-adaptive multi-modulus dividers containing div2/3 cells therein 有权
标题翻译：在其中包含div2 / 3单元的自适应多模式分频器
公开(公告)号：US09118333B1
公开(公告)日：2015-08-25
申请号：US14013599
申请日：2013-08-29
申请人： Integrated Device Technology, Inc.
发明人： Benedykt Mika , Pengfei Hu
IPC分类号： H03K21/00 , H03K23/00 , H03K23/70 , H03K23/68 , H03K23/66
CPC分类号： H03K23/70 , H03K21/00 , H03K21/023 , H03K21/38 , H03K23/00 , H03K23/667 , H03K23/68
摘要： Integrated circuit devices include programmable dividers, such as fractional-N dividers, which can utilize multi-modulus dividers (MMD) therein. A multi-modulus divider includes a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte P during an update time interval and may even fully turn off one or more of the div2/3 cells not participating in a divide-by-N operation, where N is a positive integer greater than one. The div2/3 cells are configured to include a modulus input terminal and a modulus output terminal and the chain length control operation is independent of the magnitude of the signals provided to the modulus input terminals of the div2/3 cells.
摘要翻译：集成电路设备包括可以使用其中的多模式分频器（MMD）的可编程分频器，例如分数N分频器。多模式分配器包括一个分级链div2 / 3单元，其被配置为支持链长控制操作，该操作排除在响应于链长度控制字节P 的值的变化期间产生中间除数更新时间间隔，甚至可以完全关闭不参与除N运算的一个或多个div2 / 3单元，其中N是大于1的正整数。 div2 / 3单元被配置为包括模数输入端和模输出端，并且链长控制操作与提供给div2 / 3单元的模输入端的信号的幅度无关。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式