会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明授权
    • Method of reducing delamination in the fabrication of small-pitch devices
    • 减少小间距装置制造中分层的方法
    • US08048813B2
    • 2011-11-01
    • US12326099
    • 2008-12-01
    • Chih-Yu LaiCheng-Ta WuNeng-Kuo ChenCheng-Yuan Tsai
    • Chih-Yu LaiCheng-Ta WuNeng-Kuo ChenCheng-Yuan Tsai
    • H01L21/302
    • H01L21/0337
    • A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.
    • 形成集成电路结构的方法包括提供基板; 在衬底上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层; 图案化第二硬掩模层以形成硬掩模; 并且在图案化第二硬掩模层的步骤之后,烘烤基板,第一硬掩模层和硬掩模。 在烘烤步骤之后,形成间隔层,其包括在硬掩模的顶部上的第一部分和硬掩模的相对侧壁上的第二部分和第三部分。 该方法还包括去除间隔层的第一部分; 去除硬面膜; 并且使用间隔层的第二部分和第三部分作为掩模来对第一硬掩模层进行图案化。
    • 6. 发明申请
    • Method for Forming Interconnect Structures
    • 形成互连结构的方法
    • US20100022084A1
    • 2010-01-28
    • US12179991
    • 2008-07-25
    • Neng-Kuo ChenKuo-Hwa TzengCheng-Yuan Tsai
    • Neng-Kuo ChenKuo-Hwa TzengCheng-Yuan Tsai
    • H01L21/4763
    • H01L21/7681H01L21/02134H01L21/02137H01L21/02164H01L21/022H01L21/02203H01L21/02274H01L21/31608H01L21/76801
    • Methods of fabricating interconnect structures in a semiconductor integrated circuit (IC) are presented. A preferred embodiment comprises forming interconnect lines and vias through a dual-damascenes process. It includes forming a via dielectric layer, an etch stop layer directly over the via dielectric layer, and a trench dielectric layer over the etch stop layer. The etch stop layer is patterned through a first photolithography and etch process to form openings in the etch stop layer, prior to the formation of the trench dielectric layer. A second photolithography and etch process is performed after formation of the trench dielectric layer to create trench openings in the trench dielectric layer and via openings in the via dielectric layer, where the patterned etch stop layer acts as a hard-mask in forming vias in the via dielectric layer.
    • 提出了在半导体集成电路(IC)中制造互连结构的方法。 优选实施例包括通过双重镶嵌工艺形成互连线和通孔。 它包括形成通孔电介质层,直接在通孔电介质层上的蚀刻停止层,以及在蚀刻停止层上的沟槽电介质层。 在形成沟槽电介质层之前,蚀刻停止层通过第一光刻和蚀刻工艺图案化以在蚀刻停止层中形成开口。 在形成沟槽电介质层之后执行第二光刻和蚀刻工艺,以在沟槽电介质层和通孔电介质层中的通孔开口形成沟槽开口,其中图案化蚀刻停止层在形成通孔中用作硬掩模 通过电介质层。
    • 7. 发明申请
    • Hybrid Gap-fill Approach for STI Formation
    • 用于STI形成的混合间隙填充方法
    • US20090127648A1
    • 2009-05-21
    • US11969168
    • 2008-01-03
    • Neng-Kuo ChenChih-Hsiang ChangCheng-Yuan TsaiWei-Chung WangChun-Te Li
    • Neng-Kuo ChenChih-Hsiang ChangCheng-Yuan TsaiWei-Chung WangChun-Te Li
    • H01L23/58H01L21/762
    • H01L21/76232
    • A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a first deposition step to fill a first dielectric material into the opening using a first deposition method. The first deposition method has a bottom deposition rate substantially greater than a sidewall deposition rate. The method further includes isotropically etching the first dielectric material, wherein at least a bottom portion of the first dielectric material remains after the etching; and performing a second deposition step to fill a remaining portion of the opening with a second dielectric material. The first deposition method may be a high-density plasma chemical vapor deposition. The second deposition method may be a high-aspect ratio process.
    • 提供了形成浅沟槽隔离区域的方法。 该方法包括:提供包括顶表面的半导体衬底; 形成从所述顶表面延伸到所述半导体衬底中的开口; 执行第一沉积步骤以使用第一沉积方法将第一介电材料填充到所述开口中。 第一沉积方法具有基本上大于侧壁沉积速率的底部沉积速率。 该方法还包括各向同性蚀刻第一介电材料,其中在蚀刻之后第一介电材料的至少底部部分保留; 以及执行第二沉积步骤以用第二电介质材料填充所述开口的剩余部分。 第一沉积方法可以是高密度等离子体化学气相沉积。 第二沉积方法可以是高纵横比法。