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1. 发明申请

US20130249506A1 Integrated Switch-Capacitor DC-DC Converter and Method Thereof 有权
公开(公告)号：US20130249506A1
公开(公告)日：2013-09-26
申请号：US13426720
申请日：2012-03-22
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： G05F1/46
CPC分类号： G05F1/462 , H02M3/07 , H02M2003/077 , Y10T307/406
摘要： An integrated switch-capacitor DC-DC converter and method are disclosed. In an embodiment, a converter includes a switch-capacitor network for receiving a source voltage and outputting a load voltage to a load circuit in accordance with a N-bit control code and a plurality of phase clocks, wherein N is an integer greater than 1, a load capacitor for holding the load voltage, a feedback network for generating a feedback voltage proportional to the load voltage, and a controller for receiving the feedback voltage and a reference voltage and outputting the N-bit control code in accordance with a clock phase of the plurality of phase clocks.

2. 发明授权

US08487702B2 Transimpedance amplifier and method thereof 有权
标题翻译：互阻放大器及其方法
公开(公告)号：US08487702B2
公开(公告)日：2013-07-16
申请号：US13238780
申请日：2011-09-21
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H03F1/22
CPC分类号： H03F3/082
摘要： A transimpedance method and apparatus are provided. In one implementation an apparatus includes a common-gate amplifier for receiving a first current from a first circuit node and outputting a second current to a second circuit node, and a load circuit coupled to the second circuit node, the load circuit comprising a diode-connected MOS (metal-oxide semiconductor field effect transistor), wherein a gate terminal of the MOS is coupled to a drain terminal of the MOS via a resistor. In one embodiment, a current-mode input is injected to the first circuit node and the apparatus further comprises a biasing circuit for outputting a substantially constant current to the first circuit node.
摘要翻译：提供了一种跨阻抗方法和装置。在一个实现中，一种装置包括共栅放大器，用于从第一电路节点接收第一电流并将第二电流输出到第二电路节点，以及耦合到第二电路节点的负载电路，负载电路包括二极管 - 连接的MOS（金属氧化物半导体场效应晶体管），其中MOS的栅极端子经由电阻器耦合到MOS的漏极端子。在一个实施例中，电流模式输入被注入到第一电路节点，并且该装置还包括用于向第一电路节点输出基本恒定的电流的偏置电路。

3. 发明授权

US08471630B2 Fast settling reference voltage buffer and method thereof 有权
标题翻译：快速稳定参考电压缓冲器及其方法
公开(公告)号：US08471630B2
公开(公告)日：2013-06-25
申请号：US13456536
申请日：2012-04-26
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H03F1/14
CPC分类号： H03F3/45071 , H03M1/002 , H03M1/44
摘要： A fast settling reference voltage buffer and method are disclosed. In one of embodiments, An apparatus comprising: an OTA (operational trans-conductance amplifier) with a positive input terminal coupled to a reference voltage, a negative input terminal coupled to a feedback node, and an output terminal coupled to a circuit node shunt to ground by a shunt capacitor via a current sensor; a tunable resistor, controlled by a control signal, coupling the circuit node to the feedback node; a load circuit coupled to the feedback node via a switch controlled by a logical signal; and a control circuit for receiving an output of the current sensor and outputting the control signal, wherein the control signal is adapted in accordance with the output of the current sensor.
摘要翻译：公开了一种快速稳定的参考电压缓冲器和方法。在一个实施例中，一种装置，包括：具有耦合到参考电压的正输入端的OTA（运算跨导放大器），耦合到反馈节点的负输入端，以及耦合到电路节点分流到通过电流传感器由分流电容器接地; 由控制信号控制的可调电阻器，将电路节点耦合到反馈节点; 经由由逻辑信号控制的开关耦合到所述反馈节点的负载电路; 以及控制电路，用于接收电流传感器的输出并输出控制信号，其中控制信号根据电流传感器的输出而适配。

4. 发明授权

US08451949B2 Clock-data recovery and method for binary signaling using low resolution ADC 有权
标题翻译：使用低分辨率ADC的二进制信号的时钟数据恢复和方法
公开(公告)号：US08451949B2
公开(公告)日：2013-05-28
申请号：US12574506
申请日：2009-10-06
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H04L27/00 , H04L27/06
CPC分类号： H04L27/063 , G11B20/10009 , G11B20/10027 , G11B20/10037 , G11B20/10046 , G11B20/10222 , G11B20/14 , G11B20/1496 , H03L7/091 , H04L7/0062 , H04L7/033
摘要： A binary signal detection based on low resolution ADC includes: a variable-gain amplifier for amplifying an input signal with a gain factor controlled by a gain setting to generate an amplified signal; an ADC for converting the amplified signal into a converter output in accordance with a timing provided by a recovered clock, wherein the converter output has N levels; a timing detection circuit for generating a timing error signal based on the converter output; a filter for filtering the timing error signal to generate a control signal; a controllable oscillator for generating the recovered clock under a control of the control voltage; an automatic gain control for processing the converter data to set the gain setting to control the gain factor; and a data recovery circuit for generate a recovered data based on the converter output.
摘要翻译：基于低分辨率ADC的二进制信号检测包括：可变增益放大器，用于通过由增益设置控制的增益因子放大输入信号以产生放大信号; ADC，用于根据恢复的时钟提供的定时将放大的信号转换成转换器输出，其中转换器输出具有N个电平; 定时检测电路，用于基于所述转换器输出产生定时误差信号; 用于对定时误差信号进行滤波以产生控制信号的滤波器; 可控振荡器，用于在控制电压的控制下产生恢复时钟; 用于处理转换器数据以设置增益设置以控制增益因子的自动增益控制; 以及数据恢复电路，用于基于转换器输出生成恢复的数据。

5. 发明申请

US20130106516A1 Fast Settling Reference Voltage Buffer and Method Thereof 有权
标题翻译：快速稳定基准电压缓冲器及其方法
公开(公告)号：US20130106516A1
公开(公告)日：2013-05-02
申请号：US13456536
申请日：2012-04-26
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H03F3/45
CPC分类号： H03F3/45071 , H03M1/002 , H03M1/44
摘要： A fast settling reference voltage buffer and method are disclosed. In one of embodiments, An apparatus comprising: an OTA (operational trans-conductance amplifier) with a positive input terminal coupled to a reference voltage, a negative input terminal coupled to a feedback node, and an output terminal coupled to a circuit node shunt to ground by a shunt capacitor via a current sensor; a tunable resistor, controlled by a control signal, coupling the circuit node to the feedback node; a load circuit coupled to the feedback node via a switch controlled by a logical signal; and a control circuit for receiving an output of the current sensor and outputting the control signal, wherein the control signal is adapted in accordance with the output of the current sensor.
摘要翻译：公开了一种快速稳定的参考电压缓冲器和方法。在一个实施例中，一种装置，包括：具有耦合到参考电压的正输入端的OTA（运算跨导放大器），耦合到反馈节点的负输入端，以及耦合到电路节点分流到通过电流传感器由分流电容器接地; 由控制信号控制的可调电阻器，将电路节点耦合到反馈节点; 经由由逻辑信号控制的开关耦合到所述反馈节点的负载电路; 以及控制电路，用于接收电流传感器的输出并输出控制信号，其中控制信号根据电流传感器的输出而适配。

6. 发明申请

US20130106515A1 METHOD AND APPARATUS OF COMMON MODE COMPENSATION FOR VOLTAGE CONTROLLED DELAY CIRCUITS 有权
标题翻译：用于电压控制延迟电路的公共模式补偿的方法和装置
公开(公告)号：US20130106515A1
公开(公告)日：2013-05-02
申请号：US13281573
申请日：2011-10-26
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H03F3/45 , H03K5/22
CPC分类号： H03L7/0995
摘要： An apparatus of common mode compensation for voltage controlled delay circuits and method are provided. In one implementation a method includes amplifying a differential input signal to generate a differential output signal using a differential pair of transistors biased by a tail current; changing the tail current by a first amount to change a circuit delay of the differential pair of transistors; generating a first compensation current and a second compensation current by using a current mirroring such that a sum of the first compensation current and the second compensation current is of a second amount that is substantially equal to the first amount; injecting the first compensation current into the first end of the differential output signal via a first coupling resistor; and injecting the second compensation current into the second end of the differential output signal via a second coupling resistor.
摘要翻译：提供了一种用于电压控制延迟电路和方法的共模补偿装置。在一个实现中，一种方法包括：使用由尾部电流偏置的差分对晶体管来放大差分输入信号以产生差分输出信号; 将尾部电流改变第一量以改变晶体管的差分对的电路延迟; 通过使用电流镜像来产生第一补偿电流和第二补偿电流，使得第一补偿电流和第二补偿电流之和为基本上等于第一量的第二量; 经由第一耦合电阻将第一补偿电流注入差分输出信号的第一端; 以及经由第二耦合电阻将所述第二补偿电流注入所述差分输出信号的第二端。

7. 发明授权

US08331517B2 Serial link receiver and method thereof 有权
标题翻译：串行链路接收机及其方法
公开(公告)号：US08331517B2
公开(公告)日：2012-12-11
申请号：US12826642
申请日：2010-06-29
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H04L7/02
CPC分类号： H03L7/06
摘要： A method and apparatus of clock recovery is disclosed. The apparatus comprising: a first delay circuit for receiving an input data signal and outputting a delayed data signal; an edge extraction circuit for outputting an edge signal by detecting a transition in the input data signal; an clock generator for generating a first clock signal based on an injection of the edge signal, wherein the first clock signal comprises a plurality of phase signals; a second delay buffer for outputting a second clock signal according to the first clock signal; a sampler for outputting a plurality of samples based on sampling the delayed data signal in accordance with the phase signals; and a decision circuit for generating a decision in accordance with the second clock signal based on the three samples and a previous decision.
摘要翻译：公开了一种时钟恢复的方法和装置。该装置包括：第一延迟电路，用于接收输入数据信号并输出延迟的数据信号; 边缘提取电路，用于通过检测输入数据信号中的转变来输出边缘信号; 时钟发生器，用于基于所述边缘信号的注入产生第一时钟信号，其中所述第一时钟信号包括多个相位信号; 第二延迟缓冲器，用于根据第一时钟信号输出第二时钟信号; 用于根据所述相位信号对延迟的数据信号进行采样来输出多个采样的采样器; 以及判定电路，用于基于三个样本和先前的判定来生成根据第二时钟信号的判定。

8. 发明授权

US08253612B2 Self-calibrating R-2R ladder and method thereof 有权
标题翻译：自校准R-2R梯及其方法
公开(公告)号：US08253612B2
公开(公告)日：2012-08-28
申请号：US12902435
申请日：2010-10-12
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/785
摘要： A method and apparatus are provided for calibrating a ladder circuit. The apparatus includes: a logic unit for receiving a first logical signal, a second logical signal, and N control bits and for outputting N alternative control bits and an additional control bit, where N is an integer greater than 1; a core circuit for receiving the N alternative control bits, the additional control bit, and a tuning word, and for outputting an output signal, wherein the core circuit comprises N−1 series elements, N shunt elements with a connectivity controlled by the N alternative control bits, respectively, and a termination element with a connectivity controlled by the additional control bit; and a calibration circuit for receiving the first logical signal, the second logical signal, and the output signal and for outputting the tuning word. When the first logical signal is 0, the apparatus operates in a normal mode and the output signal follows the N control bits; when the first logical signal is 1, the apparatus operates in a calibration mode and the output signal follows the second logical signal. When the apparatus operates in the calibration mode, the tuning word is adjusted in a closed loop manner so as to make the output signal substantially the same regardless of a value of the second logical signal.
摘要翻译：提供了用于校准梯形电路的方法和装置。该装置包括：逻辑单元，用于接收第一逻辑信号，第二逻辑信号和N个控制位，并用于输出N个替代控制位和附加控制位，其中N是大于1的整数; 用于接收N个替代控制位的核心电路，附加控制位和调谐字，并用于输出输出信号，其中核心电路包括N-1个串联元件，N个分流元件，具有由N个备选方案控制的连接控制位，以及具有由附加控制位控制的连接的终端元件; 以及用于接收第一逻辑信号，第二逻辑信号和输出信号并用于输出调谐字的校准电路。当第一逻辑信号为0时，装置以正常模式工作，输出信号遵循N个控制位; 当第一逻辑信号为1时，装置在校准模式下操作，并且输出信号遵循第二逻辑信号。当设备在校准模式下操作时，以闭环方式调整调谐字，使得输出信号基本上相同，而与第二逻辑信号的值无关。

9. 发明授权

US08143930B2 Method and apparatus for amplifying a time difference 有权
标题翻译：用于放大时差的方法和装置
公开(公告)号：US08143930B2
公开(公告)日：2012-03-27
申请号：US12394888
申请日：2009-02-27
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H03K3/00
CPC分类号： H03K5/13 , H03K2005/00234
摘要： Various methods and apparatus can be used for amplifying a time interval in a variety of applications. In an embodiment, a feedback device is implemented in a time amplifier in conjunction with an output device of the time amplifier.
摘要翻译：可以使用各种方法和装置来放大各种应用中的时间间隔。在一个实施例中，反馈装置在时间放大器中结合时间放大器的输出装置实现。

10. 发明授权

US08120572B2 Liquid crystal display panel 有权
标题翻译：液晶显示面板
公开(公告)号：US08120572B2
公开(公告)日：2012-02-21
申请号：US12124213
申请日：2008-05-21
申请人： Cheng-Jen Chu , Li-Nien Lin , Chia-Liang Lin
发明人： Cheng-Jen Chu , Li-Nien Lin , Chia-Liang Lin
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G2300/0456 , G09G2310/0205
摘要： In a liquid crystal display panel, each pixel unit includes first and second pixels, a first scan line coupled to the first pixel, and a second scan line coupled to the second pixel via an active element. During a first scan period, the first scan line, the second scan line and the active element are all activated to write a first voltage to the first and second pixels. During a second scan period, the first scan line remains activated but the second scan line and the active element are deactivated so that a second voltage is written to the first sub-pixel and the second sub-pixel is maintained at the first voltage.
摘要翻译：在液晶显示面板中，每个像素单元包括第一和第二像素，耦合到第一像素的第一扫描线和经由有源元件耦合到第二像素的第二扫描线。在第一扫描周期期间，第一扫描线，第二扫描线和有源元件都被激活以将第一电压写入第一和第二像素。在第二扫描周期期间，第一扫描线保持激活，但是第二扫描线和有源元件被去激活，使得第二电压被写入第一子像素，而第二子像素被保持在第一电压。

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