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1. 发明申请

US20190149238A1 PAM4 TRANSCEIVERS FOR HIGH-SPEED COMMUNICATION 审中-公开
公开(公告)号：US20190149238A1
公开(公告)日：2019-05-16
申请号：US16249642
申请日：2019-01-16
申请人： INPHI CORPORATION
发明人： Karthik GOPALAKRISHNAN , Jamal RIANI , Arun TIRUVUR
IPC分类号： H04B10/40 , H04L25/00 , H04L25/49 , H04L7/033 , H04L7/00 , H03L7/23 , H03L7/197 , H03L7/099 , H03L7/093 , H03K19/0185 , H03K5/00 , H04B10/54
CPC分类号： H04B10/40 , H03K5/00 , H03K19/018521 , H03L7/093 , H03L7/099 , H03L7/1976 , H03L7/23 , H03L2207/06 , H04B10/541 , H04L7/0037 , H04L7/0062 , H04L7/0079 , H04L7/0087 , H04L7/0091 , H04L7/0331 , H04L25/00 , H04L25/49
摘要： The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

2. 发明申请

US20180131443A1 PAM4 TRANSCEIVERS FOR HIGH-SPEED COMMUNICATION 审中-公开
公开(公告)号：US20180131443A1
公开(公告)日：2018-05-10
申请号：US15809902
申请日：2017-11-10
申请人： INPHI CORPORATION
发明人： Karthik Gopalakrishnan , Jamal RIANI , Arun TIRUVUR
IPC分类号： H04B10/40 , H04B10/54 , H04L7/00 , H04L7/033
CPC分类号： H04B10/40 , H03K5/00 , H03K19/018521 , H03L7/093 , H03L7/099 , H03L7/1976 , H03L7/23 , H03L2207/06 , H04B10/541 , H04L7/0037 , H04L7/0062 , H04L7/0079 , H04L7/0087 , H04L7/0091 , H04L7/0331 , H04L25/00
摘要： The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

3. 发明授权

US09917685B2 Eye width measurement and margining in communication systems 有权
公开(公告)号：US09917685B2
公开(公告)日：2018-03-13
申请号：US15614470
申请日：2017-06-05
申请人： Intel Corporation
发明人： Dima Hammad , Vadim Levin , Amir Laufer , Ron Bar-Lev , Noam Familia , Itamar Levin
IPC分类号： H04L7/00 , H04L1/00 , H03L7/107 , H03L7/093 , H03L7/08 , H04L1/20 , H04L1/24
CPC分类号： H04L7/0054 , H03L7/0807 , H03L7/093 , H03L7/1075 , H04L1/00 , H04L1/203 , H04L1/24 , H04L7/0016 , H04L7/0062 , H04L7/0079
摘要： Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

4. 发明授权

US09793903B1 Device and method for recovering clock and data 有权
公开(公告)号：US09793903B1
公开(公告)日：2017-10-17
申请号：US15264574
申请日：2016-09-13
申请人： GLOBAL UNICHIP CORPORATION , TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Yen-Chung Chen , Wen-Juh Kang , Chen-Yang Pan
IPC分类号： H04L7/00 , H03L7/08 , H03L7/091 , H03K19/21 , H04L7/033
CPC分类号： H03L7/0807 , H03K19/21 , H03K21/38 , H03L7/091 , H03L7/093 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0338
摘要： A clock and data recovery device includes a data sampling module, a phase detection circuit, a frequency estimator, a clock generation module, and a data recovery module. The data sampling module samples input data according to first clock signals to generate data values, in which phases of the first clock signals are different from one another. The phase detection circuit detects a phase error of the input data according to at least one second clock signal, to generate an error signal. The frequency estimator generates an adjustment signal according to the error signal, a phase threshold value, and a frequency threshold value. The clock generation module generates the first clock signals and the at least one second clock signal according to the adjustment signal and a reference clock signal. The data recovery module generates recovered data corresponding to the input data according to the data values.

5. 发明授权

US09780796B2 Timing recovery for digital receiver with interleaved analog-to-digital converters 有权
公开(公告)号：US09780796B2
公开(公告)日：2017-10-03
申请号：US15271096
申请日：2016-09-20
申请人： eTopus Technology Inc.
发明人： Yu Kou
IPC分类号： H03L7/08 , H04L7/00 , H03M1/06 , H03L7/091 , H03L7/093 , H03L7/14 , H04L7/033 , H03M1/12
CPC分类号： H03L7/0807 , H03L7/091 , H03L7/093 , H03L7/146 , H03M1/0624 , H03M1/1215 , H04L7/0016 , H04L7/0062 , H04L7/0079 , H04L7/0331
摘要： A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.

6. 发明申请

US20170099132A1 Receiver with enhanced clock and data recovery 有权
公开(公告)号：US20170099132A1
公开(公告)日：2017-04-06
申请号：US15209529
申请日：2016-07-13
申请人： Rambus Inc.
发明人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
IPC分类号： H04L7/00 , H04L7/033
CPC分类号： H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
摘要： A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

7. 发明授权

US09571308B1 High speed transceiver 有权
标题翻译：高速收发器
公开(公告)号：US09571308B1
公开(公告)日：2017-02-14
申请号：US14581934
申请日：2014-12-23
申请人： ClariPhy Communications, Inc.
发明人： Marcel Louis Lugthart , Jeffrey Zachan , Linghsiao Jerry Wang , Paul Voois , Neel H. Patel , Norman L. Swenson , Scott Powell
IPC分类号： H04L27/18 , H04L25/03 , H04L27/38 , H04L5/14 , H04B1/40
CPC分类号： H04L7/0037 , H03M5/12 , H04B1/40 , H04L5/14 , H04L7/0016 , H04L7/0054 , H04L7/0062 , H04L7/0087 , H04L7/02 , H04L7/033 , H04L25/03 , H04L25/03006 , H04L25/14 , H04L27/02 , H04L27/38 , H04L47/70
摘要： Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.
摘要翻译：这里描述了用于高速通信的系统和方法。在某些方面，系统和方法包括用于重新定时，多路复用，解复用和传输数据的创新收发器架构和技术。系统和方法可用于实现不同电子设备，计算设备，存储设备和外围设备之间可靠的高速点对点通信。

8. 发明授权

US09425950B2 Sampling clock adjustment for an analog to digital converter of a receiver 有权
标题翻译：接收机模数转换器的采样时钟调整
公开(公告)号：US09425950B2
公开(公告)日：2016-08-23
申请号：US14572676
申请日：2014-12-16
申请人： eTopus Technology Inc.
发明人： Yu Kou
IPC分类号： H04L7/027 , H04L7/00
CPC分类号： H04L7/0029 , H04L7/0062 , H04L7/04
摘要： A receiver for high speed communications. The receiver includes an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock. A finite impulse response filter generates at least one filtered input signal based on the digital input signal. A data decision circuit recovers data based on the filtered input signal. The filtered input signal and the recovered data can be provided to a feedback loop to determine a timing error of the sampling clock, which is then used to generate the sampling clock.
摘要翻译：用于高速通信的接收机。该接收器包括模数转换器，用于在由采样时钟控制的定时处将模拟输入信号转换成至少一个数字输入信号。有限脉冲响应滤波器基于数字输入信号产生至少一个滤波输入信号。数据判定电路根据经滤波的输入信号恢复数据。经过滤波的输入信号和恢复的数据可以提供给反馈回路，以确定采样时钟的定时误差，然后采样时钟用于产生采样时钟。

9. 发明授权

US09379878B1 Deskew in a high speed link 有权
标题翻译：在高速链接中的偏斜校正
公开(公告)号：US09379878B1
公开(公告)日：2016-06-28
申请号：US14581979
申请日：2014-12-23
申请人： ClariPhy Communications, Inc.
发明人： Marcel Louis Lugthart , Jeffrey Zachan , Linghsiao Jerry Wang
IPC分类号： H04L7/00
CPC分类号： H04L7/0037 , H03M5/12 , H04B1/40 , H04L5/14 , H04L7/0016 , H04L7/0054 , H04L7/0062 , H04L7/0087 , H04L7/02 , H04L7/033 , H04L25/03 , H04L25/03006 , H04L25/14 , H04L27/02 , H04L27/38 , H04L47/70
摘要： Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.
摘要翻译：这里描述了用于高速通信的系统和方法。在某些方面，系统和方法包括用于重新定时，多路复用，解复用和传输数据的创新收发器架构和技术。系统和方法可用于实现不同电子设备，计算设备，存储设备和外围设备之间可靠的高速点对点通信。

10. 发明授权

US09313017B1 Baud-rate CDR circuit and method for low power applications 有权
标题翻译：波特率CDR电路和低功耗应用的方法
公开(公告)号：US09313017B1
公开(公告)日：2016-04-12
申请号：US14737330
申请日：2015-06-11
申请人： Xilinx, Inc.
发明人： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Zhaoyin D. Wu , Kun-Yung Chang
IPC分类号： H04L7/00 , H04L7/033
CPC分类号： H04L7/0087 , H04L7/0025 , H04L7/0062 , H04L25/03
摘要： In an example, a clock data recovery (CDR) circuit for a receiver includes a timing error detector circuit, a loop filter, and a phase interpolator. The timing error detector circuit is coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver. The timing error detector circuit is operable to generate both a timing error value and an estimated waveform value per symbol based on the data samples and the error samples. The loop filter is coupled to the timing error detector to receive timing error values. The phase interpolator is coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to generate a control signal to adjust a sampling phase used to generate the data samples and the error samples.
摘要翻译：在一个示例中，用于接收机的时钟数据恢复（CDR）电路包括定时误差检测器电路，环路滤波器和相位内插器。定时误差检测器电路被耦合以以波特率接收由接收器接收的符号的数据样本和误差样本。定时误差检测器电路可操作以基于数据样本和误差样本同时产生每个符号的定时误差值和估计波形值。环路滤波器耦合到定时误差检测器以接收定时误差值。相位内插器耦合到环路滤波器以接收滤波的定时误差值，相位插值器可操作以产生控制信号以调整用于生成数据样本和误差采样的采样相位。

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