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1. 发明申请

US20130175689A1 BONDING PAD AND METHOD OF MAKING SAME 有权
标题翻译：粘接垫及其制造方法
公开(公告)号：US20130175689A1
公开(公告)日：2013-07-11
申请号：US13343940
申请日：2012-01-05
申请人： Chiang-Ming CHUANG , Chun Che HUANG , Shih-Chieh CHANG
发明人： Chiang-Ming CHUANG , Chun Che HUANG , Shih-Chieh CHANG
IPC分类号： H01L23/488 , H01L21/285
CPC分类号： H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/05124 , H01L2224/05186 , H01L2224/05624 , H01L2924/01013 , H01L2924/0132 , H01L2924/12042 , H01L2924/01029 , H01L2924/00
摘要： The description relates to a bonding pad for a semiconductor device deposited. The first region comprising aluminum deposited at a high temperature having a large grain size. The second region comprising aluminum deposited at a lower temperature having a smaller grain size.
摘要翻译：该描述涉及沉积的用于半导体器件的焊盘。第一区域包括在高温下沉积的具有大的晶粒尺寸的铝。第二区域包括在较低温度下沉积的具有较小晶粒尺寸的铝。

2. 发明申请

US20070284678A1 Methods of Manufacturing Metal-Silicide Features 有权
标题翻译：制造金属硅化物特性的方法
公开(公告)号：US20070284678A1
公开(公告)日：2007-12-13
申请号：US11838376
申请日：2007-08-14
申请人： Chen-Tung Lin , Chih-Wei Chang , Chii-Ming Wu , Mei-Yun Wang , Chiang-Ming Chuang , Shau-Lin Shue
发明人： Chen-Tung Lin , Chih-Wei Chang , Chii-Ming Wu , Mei-Yun Wang , Chiang-Ming Chuang , Shau-Lin Shue
IPC分类号： H01L21/3205 , H01L29/45
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/28097 , H01L21/28525 , H01L21/76877 , H01L21/76889 , H01L23/485 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.
摘要翻译：一种制造微电子器件的方法，包括形成围绕位于衬底上的虚拟特征的介电层，去除虚拟特征以在电介质层中形成开口，以及通过金属沉积工艺形成符合开口的金属硅化物层使用包括金属和硅的靶。然后可以将金属硅化物层退火。

3. 发明申请

US20070102769A1 Dual SOI structure 有权
标题翻译：双重SOI结构
公开(公告)号：US20070102769A1
公开(公告)日：2007-05-10
申请号：US11268914
申请日：2005-11-08
申请人： Chiang-Ming Chuang , Kuang-Hsin Chen , I-Lu Wu
发明人： Chiang-Ming Chuang , Kuang-Hsin Chen , I-Lu Wu
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure having a hybrid crystal orientation is provided. The semiconductor structure includes an insulator layer, e.g., a buried oxide (BOX), on a first semiconductor layer, and a second semiconductor layer on the buried oxide, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively. A first region of the second semiconductor layer is replaced with an epitaxially grown layer of the first semiconductor layer, thereby providing a substrate having a first region with a first crystal orientation and a second region with a second crystal orientation. An isolation structure is formed to isolate the first and second regions. Thereafter, NMOS and PMOS transistors may be formed on the substrate in the region having the crystal orientation that is the most appropriate.
摘要翻译：提供具有混合晶体取向的半导体结构。所述半导体结构包括在第一半导体层上的绝缘体层，例如掩埋氧化物（BOX）和所述掩埋氧化物上的第二半导体层，其中所述第一和第二半导体层分别具有第一和第二晶体取向。用第一半导体层的外延生长层代替第二半导体层的第一区域，从而提供具有第一晶体取向的第一区域和具有第二晶体取向的第二区域的衬底。形成隔离结构以隔离第一和第二区域。此后，可以在具有最合适的晶体取向的区域中的衬底上形成NMOS和PMOS晶体管。

4. 发明申请

US20070090462A1 Silicided regions for NMOS and PMOS devices 有权
标题翻译：用于NMOS和PMOS器件的硅化区域
公开(公告)号：US20070090462A1
公开(公告)日：2007-04-26
申请号：US11248555
申请日：2005-10-12
申请人： Chii-Ming Wu , Chiang-Ming Chuang , Chih-Wei Chang
发明人： Chii-Ming Wu , Chiang-Ming Chuang , Chih-Wei Chang
IPC分类号： H01L29/78
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device having an NMOS and a PMOS device formed thereon is provided. The NMOS device has additional spacers formed alongside the gate electrode to allow the silicide region to be formed farther away from the gate electrode. By placing the silicide region farther away from the gate electrode, the effects of the lateral encroachment of the silicide region under the spacers is reduced, particularly the leakage. A method of forming the semiconductor device may include forming a plurality of spacers alongside the gate electrodes of a PMOS and an NMOS device, and one or more implants may be performed to implant impurities into the source/drain regions of the PMOS and NMOS devices. One or more of the spacers alongside the gate electrode of the PMOS device may be selectively removed. Thereafter, the source/drain regions may be silicided.
摘要翻译：提供了一种其上形成有NMOS和PMOS器件的半导体器件。 NMOS器件具有在栅电极旁边形成的附加间隔物，以允许硅化物区域远离栅电极形成。通过将硅化物区域放置在更远离栅电极的位置，减少了间隔物下方的硅化物区域的横向侵蚀的影响，特别是泄漏。形成半导体器件的方法可以包括在PMOS和NMOS器件的栅电极旁边形成多个间隔物，并且可以执行一个或多个注入以将杂质注入到PMOS和NMOS器件的源极/漏极区域中。可以选择性地去除与PMOS器件的栅电极旁边的一个或多个间隔物。此后，源极/漏极区域可以被硅化。

5. 发明授权

US07687861B2 Silicided regions for NMOS and PMOS devices 有权
标题翻译：用于NMOS和PMOS器件的硅化区域
公开(公告)号：US07687861B2
公开(公告)日：2010-03-30
申请号：US11248555
申请日：2005-10-12
申请人： Chii-Ming Wu , Chiang-Ming Chuang , Chih-Wei Chang
发明人： Chii-Ming Wu , Chiang-Ming Chuang , Chih-Wei Chang
IPC分类号： H01L27/092
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device having an NMOS and a PMOS device formed thereon is provided. The NMOS device has additional spacers formed alongside the gate electrode to allow the silicide region to be formed farther away from the gate electrode. By placing the silicide region farther away from the gate electrode, the effects of the lateral encroachment of the silicide region under the spacers is reduced, particularly the leakage. A method of forming the semiconductor device may include forming a plurality of spacers alongside the gate electrodes of a PMOS and an NMOS device, and one or more implants may be performed to implant impurities into the source/drain regions of the PMOS and NMOS devices. One or more of the spacers alongside the gate electrode of the PMOS device may be selectively removed. Thereafter, the source/drain regions may be silicided.
摘要翻译：提供了一种其上形成有NMOS和PMOS器件的半导体器件。 NMOS器件具有在栅电极旁边形成的附加间隔物，以允许硅化物区域远离栅电极形成。通过将硅化物区域放置在更远离栅电极的位置，减少了间隔物下方的硅化物区域的横向侵蚀的影响，特别是泄漏。形成半导体器件的方法可以包括在PMOS和NMOS器件的栅电极旁边形成多个间隔物，并且可以执行一个或多个注入以将杂质注入到PMOS和NMOS器件的源极/漏极区域中。可以选择性地去除与PMOS器件的栅电极旁边的一个或多个间隔物。此后，源极/漏极区域可以被硅化。

6. 发明授权

US07534671B2 Method for integrally forming an electrical fuse device and a MOS transistor 有权
标题翻译：一种形成电熔丝装置和MOS晶体管的方法
公开(公告)号：US07534671B2
公开(公告)日：2009-05-19
申请号：US12058664
申请日：2008-03-29
申请人： Chiang-Ming Chuang , Liang-Kai Han
发明人： Chiang-Ming Chuang , Liang-Kai Han
IPC分类号： H01L21/338 , H01L21/336
CPC分类号： H01L27/0629 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.
摘要翻译：在半导体衬底上整体形成金属氧化物半导体（MOS）器件和电熔丝器件的方法包括以下步骤。在半导体衬底上形成隔离结构。绝缘层沉积在隔离结构和半导体衬底上。金属层沉积在电介质层上。多晶硅层沉积在金属层上。电介质层，金属层和多晶硅层被图案化为隔离结构上的电介质层，金属层和多晶硅层的第一堆叠，用作电熔丝器件，以及介电层的第二堆叠，半导体衬底上的金属层和多晶硅层，用作MOS器件的栅极。

7. 发明授权

US08796851B2 Bonding pad and method of making same 有权
标题翻译：粘合垫及其制作方法
公开(公告)号：US08796851B2
公开(公告)日：2014-08-05
申请号：US13343940
申请日：2012-01-05
申请人： Chiang-Ming Chuang , Chun Che Huang , Shih-Chieh Chang
发明人： Chiang-Ming Chuang , Chun Che Huang , Shih-Chieh Chang
IPC分类号： H01L23/48
CPC分类号： H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/05124 , H01L2224/05186 , H01L2224/05624 , H01L2924/01013 , H01L2924/0132 , H01L2924/12042 , H01L2924/01029 , H01L2924/00
摘要： The description relates to a bonding pad for a semiconductor device deposited. The first region comprising aluminum deposited at a high temperature having a large grain size. The second region comprising aluminum deposited at a lower temperature having a smaller grain size.
摘要翻译：该描述涉及沉积的用于半导体器件的焊盘。第一区域包括在高温下沉积的具有大的晶粒尺寸的铝。第二区域包括在较低温度下沉积的具有较小晶粒尺寸的铝。

8. 发明申请

US20100314698A1 METHODS OF MANUFACTURING METAL-SILICIDE FEATURES 有权
公开(公告)号：US20100314698A1
公开(公告)日：2010-12-16
申请号：US12861358
申请日：2010-08-23
申请人： Chen-Tung Lin , Chih-Wei Chang , Chii-Ming Wu , Mei-Yun Wang , Chiang-Ming Chuang , Shau-Lin Shue
发明人： Chen-Tung Lin , Chih-Wei Chang , Chii-Ming Wu , Mei-Yun Wang , Chiang-Ming Chuang , Shau-Lin Shue
IPC分类号： H01L29/78
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/28097 , H01L21/28525 , H01L21/76877 , H01L21/76889 , H01L23/485 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.

9. 发明授权

US07781316B2 Methods of manufacturing metal-silicide features 有权
标题翻译：金属硅化物的制造方法
公开(公告)号：US07781316B2
公开(公告)日：2010-08-24
申请号：US11838376
申请日：2007-08-14
申请人： Chen-Tung Lin , Chih-Wei Chang , Chii-Ming Wu , Mei-Yun Wang , Chiang-Ming Chuang , Shau-Lin Shue
发明人： Chen-Tung Lin , Chih-Wei Chang , Chii-Ming Wu , Mei-Yun Wang , Chiang-Ming Chuang , Shau-Lin Shue
IPC分类号： H01L21/44 , H01L21/28 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/28097 , H01L21/28525 , H01L21/76877 , H01L21/76889 , H01L23/485 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.
摘要翻译：一种制造微电子器件的方法，包括形成围绕位于衬底上的虚拟特征的介电层，去除虚拟特征以在电介质层中形成开口，以及通过金属沉积工艺形成符合开口的金属硅化物层使用包括金属和硅的靶。然后可以将金属硅化物层退火。

10. 发明申请

US20080182373A1 Method for Integrally Forming an Electrical Fuse Device and a MOS Transistor 有权
标题翻译：用于整体形成电保险丝器件和MOS晶体管的方法
公开(公告)号：US20080182373A1
公开(公告)日：2008-07-31
申请号：US12058664
申请日：2008-03-29
申请人： Chiang-Ming Chuang , Liang-Kai Han
发明人： Chiang-Ming Chuang , Liang-Kai Han
IPC分类号： H01L21/8234
CPC分类号： H01L27/0629 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.
摘要翻译：在半导体衬底上整体形成金属氧化物半导体（MOS）器件和电熔丝器件的方法包括以下步骤。在半导体衬底上形成隔离结构。绝缘层沉积在隔离结构和半导体衬底上。金属层沉积在电介质层上。多晶硅层沉积在金属层上。电介质层，金属层和多晶硅层被图案化为隔离结构上的电介质层，金属层和多晶硅层的第一堆叠，用作电熔丝器件，以及介电层的第二堆叠，半导体衬底上的金属层和多晶硅层，用作MOS器件的栅极。

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