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1. 发明申请

US20100273324A1 METHODS OF MANUFACTURING METAL-SILICIDE FEATURES 有权
标题翻译：制备金属硅化物特性的方法
公开(公告)号：US20100273324A1
公开(公告)日：2010-10-28
申请号：US12833595
申请日：2010-07-09
申请人： Chen-Tung Lin , Chih-Wei Chang , Chii-Ming Wu , Mei-Yun Wang , Chiang-Ming Chuang , Shau-Lin Shue
发明人： Chen-Tung Lin , Chih-Wei Chang , Chii-Ming Wu , Mei-Yun Wang , Chiang-Ming Chuang , Shau-Lin Shue
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/28097 , H01L21/28525 , H01L21/76877 , H01L21/76889 , H01L23/485 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.
摘要翻译：一种制造微电子器件的方法，包括形成围绕位于衬底上的虚拟特征的介电层，去除所述虚拟特征以在所述电介质层中形成开口，以及形成符合所述开口的金属硅化物层。然后可以将金属硅化物层退火。

2. 发明授权

US07678694B2 Method for fabricating semiconductor device with silicided gate 有权
标题翻译：用硅化物栅极制造半导体器件的方法
公开(公告)号：US07678694B2
公开(公告)日：2010-03-16
申请号：US11787842
申请日：2007-04-18
申请人： Mei-Yun Wang , Cheng-Chen Calvin Hsueh
发明人： Mei-Yun Wang , Cheng-Chen Calvin Hsueh
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device having a silicided gate that is directed to forming the silicided structures while maintaining gate-dielectric integrity. Initially, a gate structure has, preferably, a poly gate electrode separated from a substrate by a gate dielectric and a metal layer is then deposited over at least the poly gate electrode. The fabrication environment is placed at an elevated temperature. The gate structure may be one of two gate structures included in a dual gate device such as a CMOS device, in which case the respective gates may be formed at different heights (thicknesses) to insure that the silicide forms to the proper phase. The source and drain regions are preferably silicided as well, but in a separate process performed while the gate electrodes are protected by, for example a cap of photoresist or a hardmask structure.
摘要翻译：一种用于制造半导体器件的方法，该半导体器件具有硅化物栅极，其被引导以形成硅化物结构，同时保持栅极 - 电介质完整性。最初，栅极结构优选地具有通过栅极电介质从衬底分离的多晶硅栅极，然后在至少多晶硅栅极上沉积金属层。制造环境放置在高温下。栅极结构可以是包括在诸如CMOS器件的双栅极器件中的两个栅极结构之一，在这种情况下，各个栅极可以形成在不同的高度（厚度），以确保硅化物形成适当的相位。源极和漏极区域也优选是硅化的，但是在通过例如光致抗蚀剂或硬掩模结构的盖保护栅电极的同时进行的单独工艺。

3. 发明授权

US07105439B2 Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology 有权
公开(公告)号：US07105439B2
公开(公告)日：2006-09-12
申请号：US10607496
申请日：2003-06-26
申请人： Chih-Wei Chang , Mei-Yun Wang , Shau-Lin Shue , Mong-Song Liang
发明人： Chih-Wei Chang , Mei-Yun Wang , Shau-Lin Shue , Mong-Song Liang
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/336
CPC分类号： H01L21/28518 , H01L29/4941 , H01L29/665 , H01L29/7833
摘要： A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-layer to a bi-silicide film having a cobalt-rich silicide portion and a nickel-rich silicide portion.

4. 发明申请

US20050280118A1 Methods of manufacturing metal-silicide features 有权
标题翻译：金属硅化物的制造方法
公开(公告)号：US20050280118A1
公开(公告)日：2005-12-22
申请号：US10872343
申请日：2004-06-18
申请人： Chen-Tung Lin , Chih-Wei Chang , Chii-Ming Wu , Mei-Yun Wang , Chiang-Ming Chuang , Shau-Lin Shue
发明人： Chen-Tung Lin , Chih-Wei Chang , Chii-Ming Wu , Mei-Yun Wang , Chiang-Ming Chuang , Shau-Lin Shue
IPC分类号： C30B1/00 , H01L21/20 , H01L21/28 , H01L21/285 , H01L21/321 , H01L21/336 , H01L21/36 , H01L21/768 , H01L23/485 , H01L29/06
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/28097 , H01L21/28525 , H01L21/76877 , H01L21/76889 , H01L23/485 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.
摘要翻译：一种制造微电子器件的方法，包括在位于衬底上的电介质层中形成开口，形成基本上符合该开口的半导电层，以及形成基本上符合半导体层的导电层。半导体层的至少一部分通过通过导电层的注入来掺杂。然后可以对半导体层和导电层进行退火。

5. 发明申请

US20050239287A1 Silicide formation using a metal-organic chemical vapor deposited capping layer 审中-公开
标题翻译：使用金属有机化学气相沉积覆盖层的硅化物形成
公开(公告)号：US20050239287A1
公开(公告)日：2005-10-27
申请号：US10742202
申请日：2003-12-18
申请人： Mei-Yun Wang , Chih-Wei Chang , Cheng-Tung Lin , Chii-Ming Wu , Shau-Lin Shue
发明人： Mei-Yun Wang , Chih-Wei Chang , Cheng-Tung Lin , Chii-Ming Wu , Shau-Lin Shue
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/336
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A self-aligned silicide method for integrated circuit and semiconductor device fabrication wherein a metal layer is formed over one or more silicon regions of a substrate and a barrier metal layer is formed over the metal layer using a chemical vapor deposition process. The temperature at which the chemical vapor deposition process is performed causes the metal layer to react with the one or more silicon regions of the substrate to form a metal-silicide film over each of the silicon regions.
摘要翻译：一种用于集成电路和半导体器件制造的自对准硅化物方法，其中在衬底的一个或多个硅区域上形成金属层，并且使用化学气相沉积工艺在金属层上形成阻挡金属层。进行化学气相沉积工艺的温度导致金属层与衬底的一个或多个硅区域反应，以在每个硅区域上形成金属硅化物膜。

6. 发明授权

US06884736B2 Method of forming contact plug on silicide structure 有权
标题翻译：在硅化物结构上形成接触塞的方法
公开(公告)号：US06884736B2
公开(公告)日：2005-04-26
申请号：US10265937
申请日：2002-10-07
申请人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Chin-Hwa Hsieh , Shau-Lin Shue , Chu-Yun Fu , Ju-Wang Hsu , Ming-Huan Tsai , Yuan-Hung Chiu
发明人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Chin-Hwa Hsieh , Shau-Lin Shue , Chu-Yun Fu , Ju-Wang Hsu , Ming-Huan Tsai , Yuan-Hung Chiu
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/302
CPC分类号： H01L21/76829 , H01L21/31105 , H01L21/31116 , H01L21/76802 , H01L21/76832
摘要： A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop layer. A portion of the etch stop layer immediately over a selected contact region is removed using a process that does not substantially react with the contact region, to form a contact opening. The contact opening is then filled with a conductive material to form a contact.
摘要翻译：提供一种制造半导体器件的方法。半导体元件形成在基板上。半导体元件具有至少一个硅化镍接触区，在所述元件上形成的蚀刻停止层，以及形成在所述蚀刻停止层上的绝缘层。使用基本上不与接触区域反应的方法去除在所选择的接触区域上方的蚀刻停止层的一部分，以形成接触开口。然后用导电材料填充接触开口以形成接触。

7. 发明授权

US06451701B1 Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors 有权
标题翻译：用于场效应晶体管的紧密间隔的导电线之间制造低电阻硅化物接触的方法
公开(公告)号：US06451701B1
公开(公告)日：2002-09-17
申请号：US09993068
申请日：2001-11-14
申请人： Mei-Yun Wang , Shwangming Jeng , Shau-Lin Shue
发明人： Mei-Yun Wang , Shwangming Jeng , Shau-Lin Shue
IPC分类号： H01L21425
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/31155
摘要： A method for making reliable low-resistance contacts between closely spaced FET gate electrodes having high-aspect-ratio spacings. Polysilicon gate electrodes are formed. A conformal insulating layer is deposited and anisotropically etched back to form sidewall spacers on the gate electrodes. During conventional etch-back, the etch rate of the insulating layer between the closely spaced gate electrodes is slower resulting in a residual oxide that prevents the formation of reliable low-resistance contacts. This residual oxide requires an overetch in a hydrofluoric acid solution prior to forming silicide contacts. The wet overetch results in device degradation. A nitrogen or germanium implant is used to amorphize the oxide and to increase the wet etch rate of the residual oxide. Using this amorphization the wet etch that is commonly used as a pre-clean prior to forming silicide contacts can be used to remove the residual silicon oxide without overetching. The implant also results in a smoother interface between the silicide and the silicon substrate, which results in lower sheet resistance.
摘要翻译：一种用于在具有高纵横比间隔的紧密间隔的FET栅电极之间进行可靠的低电阻接触的方法。形成多晶硅栅电极。沉积保形绝缘层并各向异性地回蚀以在栅电极上形成侧壁间隔物。在传统的回蚀期间，绝缘层在紧密间隔的栅电极之间的蚀刻速率较慢，导致残留的氧化物阻止形成可靠的低电阻触点。在形成硅化物接触之前，该残余氧化物需要在氢氟酸溶液中进行过蚀刻。湿过滤会导致设备退化。氮或锗植入物用于使氧化物非晶化并增加残余氧化物的湿蚀刻速率。使用这种非晶化，通常在形成硅化物接触之前通常用作预清洁的湿法蚀刻可以用于除去剩余的氧化硅而不进行过蚀刻。该植入物还导致硅化物和硅衬底之间更平滑的界面，这导致较低的薄层电阻。

8. 发明授权

US6096651A Key-hole reduction during tungsten plug formation 有权
标题翻译：钨丝塞形成期间的关键孔减少
公开(公告)号：US6096651A
公开(公告)日：2000-08-01
申请号：US228126
申请日：1999-01-11
申请人： Mei-Yun Wang , Chen-Hua Yu , Shau-Lin Shue
发明人： Mei-Yun Wang , Chen-Hua Yu , Shau-Lin Shue
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76865 , H01L21/76804 , H01L21/76843 , H01L21/76862
摘要： The problem of key-hole formation during the filling of small diameter via holes has been overcome by means of soft sputtering in argon after the barrier layer is in place. This sputtering step may be used twice--once to widen the mouth of a newly formed via hole, and a second time after the barrier layer is in place, thereby widening the mouth further (as well as removing oxide from the surface of the barrier layer). In an alternate optional embodiment, widening of the via hole mouth may be limited to a single sputtering step after the barrier layer has been laid down. In either case, this is followed by filling of the via hole which occurs without any key-hole formation.
摘要翻译：通过在阻挡层就位之后的氩气中的软溅射，克服了在小直径通孔填充期间形成孔洞的问题。该溅射步骤可以使用两次一次来加宽新形成的通孔的口，并且在阻挡层就位之后的第二次，从而进一步扩大口（以及从阻挡层的表面去除氧化物））。在替代的可选实施例中，通孔口的加宽可以在阻挡层被铺设之后被限制到单个溅射步骤。在任一种情况下，随后填充通孔而没有任何键孔形成。

9. 发明授权

US09252019B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US09252019B2
公开(公告)日：2016-02-02
申请号：US13222502
申请日：2011-08-31
申请人： Wen-Chi Tsai , Chia-Han Lai , Yung-Chung Chen , Mei-Yun Wang , Chii-Ming Wu , Fang-Cheng Chen , Huang-Ming Chen , Ming-Ta Lei
发明人： Wen-Chi Tsai , Chia-Han Lai , Yung-Chung Chen , Mei-Yun Wang , Chii-Ming Wu , Fang-Cheng Chen , Huang-Ming Chen , Ming-Ta Lei
IPC分类号： H01L21/768 , H01L21/285 , H01L29/417 , H01L21/02 , H01L29/66
CPC分类号： H01L29/78 , H01L21/02063 , H01L21/28512 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76814 , H01L21/76825 , H01L21/76831 , H01L21/76844 , H01L21/76855 , H01L23/485 , H01L23/535 , H01L29/41775 , H01L29/45 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.
摘要翻译：提供了一种用于形成和使用衬套的系统和方法。一个实施例包括在衬底之上的层间电介质中形成开口，并沿着开口的侧壁形成衬垫。衬套的一部分从开口的底部移除，并且可以通过衬套执行清洁过程。通过使用衬垫，可以减少或消除从清洁过程对开口侧壁的损坏。另外，衬垫可用于帮助衬底内的离子注入。

10. 发明申请

US20120012903A1 METHOD FOR MAKING A DISILICIDE 有权
标题翻译：制造杀虫剂的方法
公开(公告)号：US20120012903A1
公开(公告)日：2012-01-19
申请号：US12836026
申请日：2010-07-14
申请人： Chun-Wen NIEH , Hung-Chang HSU , Wen-Chi TSAI , Mei-Yun WANG , Chii-Ming WU , Wei-Jung LIN , Chih-Wei CHANG
发明人： Chun-Wen NIEH , Hung-Chang HSU , Wen-Chi TSAI , Mei-Yun WANG , Chii-Ming WU , Wei-Jung LIN , Chih-Wei CHANG
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/665 , H01L29/66575 , H01L29/7833
摘要： Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height.
摘要翻译：公开了制造半导体器件的方法。在源极/漏极（S / D）区域上形成富金属硅化物和/或单硅化物。向富金属硅化物和/或单硅化物提供毫秒退火以在硅化物和衬底之间的界面处形成具有有限尖峰的二硅化物。二硅化物具有可以降低电子肖特基势垒高度的添加剂。

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