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1. 发明申请

US20150219753A1 CIRCUITRY FOR AND METHOD OF GENERATING A FREQUENCY MODULATED RADAR TRANSMITTER SIGNAL, A RADAR TRANSCEIVER CIRCUIT AND A RADAR SYSTEM 有权
标题翻译：辐射频率调制雷达发射机信号的电路和方法，雷达收发器电路和雷达系统
公开(公告)号：US20150219753A1
公开(公告)日：2015-08-06
申请号：US14324322
申请日：2014-07-07
申请人： DIDIER SALLE , OLIVIER DOARE , CHRISTOPHE LANDEZ
发明人： DIDIER SALLE , OLIVIER DOARE , CHRISTOPHE LANDEZ
IPC分类号： G01S7/40 , G01S13/02
CPC分类号： G01S7/4008 , G01S7/032 , G01S13/02 , G01S13/343 , G01S13/584 , G01S13/931 , H03C3/0925
摘要： A circuitry for and a method of generating a frequency modulated radar transmitter signal are provided. The circuitry comprises a modulation signal generator for generating a modulation signal having a waveform describing a required frequency modulation of the frequency modulated radar transmitter signal and comprises a PLL circuitry for generating the frequency modulated radar transmitter signal in dependence of the modulation signal. In the PLL circuitry a controllable frequency divider controls the output frequency of the PLL circuitry in dependence of the modulation signal. The PLL circuitry further comprises a phase detector, a controllable oscillator and possibly a low pass filter. The PLL circuitry further comprises a calibration circuitry being configured to control a parameter of at least one of the phase detector and the controllable oscillator to maintain a loop gain of PLL circuitry.
摘要翻译：提供了一种生成调频雷达发射机信号的电路和方法。电路包括调制信号发生器，用于产生具有描述调频雷达发射机信号的所需频率调制的波形的调制信号，并包括用于根据调制信号产生调频雷达发射机信号的PLL电路。在PLL电路中，可控分频器根据调制信号来控制PLL电路的输出频率。 PLL电路还包括相位检测器，可控振荡器和可能的低通滤波器。 PLL电路还包括被配置为控制相位检测器和可控振荡器中的至少一个的参数以保持PLL电路的环路增益的校准电路。

2. 发明授权

US09722648B2 Integrated circuit device, electronic device and method for frequency detection 有权
公开(公告)号：US09722648B2
公开(公告)日：2017-08-01
申请号：US13985990
申请日：2011-03-01
申请人： Philippe Freitas , Olivier Doare , Valerie Escarpit , Christophe Landez , Xavier Lhuillier
发明人： Philippe Freitas , Olivier Doare , Valerie Escarpit , Christophe Landez , Xavier Lhuillier
IPC分类号： H04B1/06 , H04L25/02
CPC分类号： H04B1/06 , H04L25/0262
摘要： An integrated circuit comprises a frequency detector. The frequency detector comprises a timer state machine unit operably couplable to a timer and arranged to receive an incoming carrier signal; determine whether the incoming carrier signal comprises a valid frequency; generate a valid carrier indication when the incoming carrier signal is determined as having a valid frequency; and adjust the timer between at least a first timing mode of operation and a second timing mode of operation of the frequency detector in response to the determination.

3. 发明授权

US06407629B1 Sample and hold demodulator circuit 失效
标题翻译：采样和保持解调电路
公开(公告)号：US06407629B1
公开(公告)日：2002-06-18
申请号：US09609554
申请日：2000-06-30
申请人： Michel Burri , Christophe Landez
发明人： Michel Burri , Christophe Landez
IPC分类号： H03D100
CPC分类号： H03D5/00
摘要： In accordance with an embodiment of the invention there is provided a sample and hold demodulator circuit (200) for use in an automotive immobilizer to recover modulation information from a received modulated carrier signal (VRD). Sample and hold circuitry samples signals to recover the modulation information therein, and control circuitry (214) is coupled to the sample and hold circuitry for controlling operation thereof. The control circuitry includes shift register circuitry (252) for receiving a second received signal having a same frequency as a carrier frequency of the received modulated carrier signal and for producing at its outputs signals (SAMPLE, SAMPLE2, LATCH) for controlling operation of the sample and hold circuitry. The sample and hold demodulator circuit provides a single IC solution, allowing amplitude and phase demodulation to be performed with a single sample and hold circuit.
摘要翻译：根据本发明的实施例，提供了一种用于汽车防盗器中的采样和保持解调器电路（200），用于从接收到的调制载波信号（VRD）恢复调制信息。采样和保持电路采样信号以恢复其中的调制信息，并且控制电路（214）耦合到采样和保持电路以控制其操作。控制电路包括移位寄存器电路（252），用于接收具有与接收的调制载波信号的载波频率相同频率的第二接收信号，并在其输出端产生用于控制样本的操作的信号（SAMPLE，SAMPLE2，LATCH）并保持电路。采样和保持解调器电路提供单个IC解决方案，允许使用单个采样和保持电路进行幅度和相位解调。

4. 发明授权

US08654006B2 Integrated circuit comprising frequency generation circuitry for controlling a frequency source 有权
标题翻译：集成电路，包括用于控制频率源的频率产生电路
公开(公告)号：US08654006B2
公开(公告)日：2014-02-18
申请号：US13145122
申请日：2009-02-13
申请人： Christophe Landez , Hugues Beaulaton , Thierry Cassagnes , Stephane Colomines , Robert G. Gach , Akbar Ghazinour , Hao Li , Gilles Montoriol , Didier Salle , Pierre Savary
发明人： Christophe Landez , Hugues Beaulaton , Thierry Cassagnes , Stephane Colomines , Robert G. Gach , Akbar Ghazinour , Hao Li , Gilles Montoriol , Didier Salle , Pierre Savary
IPC分类号： G01S7/28
CPC分类号： G01S7/35 , G01S7/032 , G01S13/34 , G01S13/931 , G01S2013/9325 , H03C3/0925 , H03L7/1976
摘要： An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.
摘要翻译：集成电路包括用于控制汽车雷达系统的频率源的频率产生电路。频率产生电路包括被锁定环路（PLL），该锁相环路被配置为产生用于控制频率源的控制信号，位于PLL的反馈环路内的分数N分频器，以及可操作地耦合到分数N的频率模式控制逻辑并且被布置成通过频率控制信号来控制分数N分频器，使得PLL产生调频连续波（FMCW）控制信号。

5. 发明申请

US20130331050A1 INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE AND METHOD FOR FREQUENCY DETECTION 有权
标题翻译：集成电路设备，电子设备和频率检测方法
公开(公告)号：US20130331050A1
公开(公告)日：2013-12-12
申请号：US13985990
申请日：2011-03-01
申请人： Philippe Freitas , Olivier Doare , Valerie Escarpit , Christophe Landez , Xavier Lhuillier
发明人： Philippe Freitas , Olivier Doare , Valerie Escarpit , Christophe Landez , Xavier Lhuillier
IPC分类号： H04B1/06
CPC分类号： H04B1/06 , H04L25/0262
摘要： An integrated circuit comprises a frequency detector. The frequency detector comprises a timer state machine unit operably couplable to a timer and arranged to receive an incoming carrier signal; determine whether the incoming carrier signal comprises a valid frequency; generate a valid carrier indication when the incoming carrier signal is determined as having a valid frequency; and adjust the timer between at least a first timing mode of operation and a second timing mode of operation of the frequency detector in response to the determination.
摘要翻译：集成电路包括频率检测器。频率检测器包括可操作地耦合到定时器并被布置成接收输入载波信号的定时器状态机单元; 确定进入的载波信号是否包括有效频率; 当进入的载波信号被确定为具有有效频率时，生成有效载波指示; 并且响应于该确定，在至少第一定时操作模式和频率检测器的第二定时操作模式之间调整定时器。

6. 发明授权

US09720074B2 Circuitry for and method of generating a frequency modulated radar transmitter signal, a radar transceiver circuit and a radar system 有权
公开(公告)号：US09720074B2
公开(公告)日：2017-08-01
申请号：US14324322
申请日：2014-07-07
申请人： Didier Salle , Olivier Doare , Christophe Landez
发明人： Didier Salle , Olivier Doare , Christophe Landez
IPC分类号： G01S7/40 , G01S13/02 , G01S7/03 , G01S13/34 , H03C3/09 , G01S13/58 , G01S13/93
CPC分类号： G01S7/4008 , G01S7/032 , G01S13/02 , G01S13/343 , G01S13/584 , G01S13/931 , H03C3/0925
摘要： A circuitry for and a method of generating a frequency modulated radar transmitter signal are provided. The circuitry comprises a modulation signal generator for generating a modulation signal having a waveform describing a required frequency modulation of the frequency modulated radar transmitter signal and comprises a PLL circuitry for generating the frequency modulated radar transmitter signal in dependence of the modulation signal. In the PLL circuitry a controllable frequency divider controls the output frequency of the PLL circuitry in dependence of the modulation signal. The PLL circuitry further comprises a phase detector, a controllable oscillator and possibly a low pass filter. The PLL circuitry further comprises a calibration circuitry being configured to control a parameter of at least one of the phase detector and the controllable oscillator to maintain a loop gain of PLL circuitry.

7. 发明授权

US08564419B2 Wake-up control system and method for controlling receiver wake-up 有权
标题翻译：唤醒控制系统和控制接收机唤醒的方法
公开(公告)号：US08564419B2
公开(公告)日：2013-10-22
申请号：US13063679
申请日：2008-09-19
申请人： Laurent Gauthier , Christophe Landez
发明人： Laurent Gauthier , Christophe Landez
IPC分类号： G08C19/16
CPC分类号： H04W52/0283 , G07C2009/00373 , Y02D70/142 , Y02D70/144 , Y02D70/162 , Y02D70/26
摘要： A wake-up control system comprises a plurality of different signal analyzer units. The plurality of different signal analyzer units may process a value of a different parameter of an incoming signal received at an input of a receiver and provide a false wake-up indication for the parameter when the value of the parameter is outside an acceptance range for the value. The system further comprises an evaluation unit connected to the plurality of different signal analyzer units for receiving the false wake-up indications. The evaluation unit may provide a false wake-up parameter information identifying an identified parameter of the different parameters when a sum of the false wake-up indications is outside an occurrence range for the false wake-up indications for the identified parameter.
摘要翻译：唤醒控制系统包括多个不同的信号分析器单元。多个不同的信号分析器单元可以处理在接收机的输入处接收的输入信号的不同参数的值，并且当参数的值在该接收范围的接受范围之外时，为该参数提供假唤醒指示值。该系统还包括连接到多个不同信号分析器单元的评估单元，用于接收假唤醒指示。当假唤醒指示的和超出所识别的参数的假唤醒指示的发生范围之外时，评估单元可以提供识别不同参数的已识别参数的假唤醒参数信息。

8. 发明授权

US09197394B2 Clock for serial communication device 有权
标题翻译：串行通信设备时钟
公开(公告)号：US09197394B2
公开(公告)日：2015-11-24
申请号：US14402893
申请日：2012-05-29
申请人： Olivier Doare , Christophe Landez
发明人： Olivier Doare , Christophe Landez
IPC分类号： H04L7/04 , H04L7/00 , G06F13/42
CPC分类号： H04L7/0008 , G06F13/4291 , H04L7/04
摘要： Versatility and flexibility of integrated circuits can be accomplished by remote control via a serial interface, such as SPI. Read/write accesses to the SPI slave node can be achieved according to SPI protocol by the master node. Additionally, a state machine associated to the slave node SPI needs a local clock to exercise the control of the analog functions following a write access. The serial protocol defines a serial data word transfer to comprise a number of reserved clock cycles that are not assigned for communicating a data bit value of the data word. The slave device comprises a clock unit coupled to the serial clock line for providing a derived clock based on reserved clock cycles. The derived clock is used internally in the slave device to perform internal synchronous operations.
摘要翻译：集成电路的多功能性和灵活性可以通过串行接口（如SPI）的远程控制来实现。可以通过主节点根据SPI协议实现对SPI从节点的读/写访问。此外，与从节点SPI相关联的状态机需要本地时钟来执行写访问之后的模拟功能的控制。串行协议定义串行数据字传输以包括未分配用于传送数据字的数据位值的多个保留时钟周期。从设备包括耦合到串行时钟线的时钟单元，用于基于保留的时钟周期提供导出的时钟。派生时钟在从设备内部使用，以执行内部同步操作。

9. 发明申请

US20150163046A1 CLOCK FOR SERIAL COMMUNICATION DEVICE 有权
标题翻译：串行通信设备时钟
公开(公告)号：US20150163046A1
公开(公告)日：2015-06-11
申请号：US14402893
申请日：2012-05-29
申请人： Olivier Doare , Christophe Landez
发明人： Olivier Doare , Christophe Landez
IPC分类号： H04L7/00 , H04L7/04
CPC分类号： H04L7/0008 , G06F13/4291 , H04L7/04
摘要： Versatility and flexibility of integrated circuits can be accomplished by remote control via a serial interface, such as SPI. Read/write accesses to the SPI slave node can be achieved according to SPI protocol by the master node. Additionally, a state machine associated to the slave node SPI needs a local clock to exercise the control of the analog functions following a write access. The serial protocol defines a serial data word transfer to comprise a number of reserved clock cycles that are not assigned for communicating a data bit value of the data word. The slave device comprises a clock unit coupled to the serial clock line for providing a derived clock based on reserved clock cycles. The derived clock is used internally in the slave device to perform internal synchronous operations.
摘要翻译：集成电路的多功能性和灵活性可以通过串行接口（如SPI）的远程控制来实现。可以通过主节点根据SPI协议实现对SPI从节点的读/写访问。此外，与从节点SPI相关联的状态机需要本地时钟来执行写访问之后的模拟功能的控制。串行协议定义串行数据字传输以包括未分配用于传送数据字的数据位值的多个保留时钟周期。从设备包括耦合到串行时钟线的时钟单元，用于基于保留的时钟周期提供导出的时钟。派生时钟在从设备内部使用，以执行内部同步操作。

10. 发明申请

US20110285575A1 INTEGRATED CIRCUIT COMPRISING FREQUENCY GENERATION CIRCUITRY FOR CONTROLLING A FREQUENCY SOURCE 有权
标题翻译：包含用于控制频率源的频率发生电路的集成电路
公开(公告)号：US20110285575A1
公开(公告)日：2011-11-24
申请号：US13145122
申请日：2009-02-13
申请人： Christophe Landez , Hugues Beaulaton , Thierry Cassagnes , Stephane Colomines , Robert G. Gach , Akbar Ghazinour , Hao Li , Gilles Montoriol , Didier Salle , Pierre Savary
发明人： Christophe Landez , Hugues Beaulaton , Thierry Cassagnes , Stephane Colomines , Robert G. Gach , Akbar Ghazinour , Hao Li , Gilles Montoriol , Didier Salle , Pierre Savary
IPC分类号： G01S13/02
CPC分类号： G01S7/35 , G01S7/032 , G01S13/34 , G01S13/931 , G01S2013/9325 , H03C3/0925 , H03L7/1976
摘要： An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.
摘要翻译：集成电路包括用于控制汽车雷达系统的频率源的频率产生电路。频率产生电路包括被锁定环路（PLL），该锁相环路被配置为产生用于控制频率源的控制信号，位于PLL的反馈环路内的分数N分频器，以及可操作地耦合到分数N的频率模式控制逻辑并且被布置成通过频率控制信号来控制分数N分频器，使得PLL产生调频连续波（FMCW）控制信号。

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