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1. 发明授权

US07469399B2 Semi-flattened pin optimization process for hierarchical physical designs 失效
标题翻译：半平面针脚优化过程，用于分层物理设计
公开(公告)号：US07469399B2
公开(公告)日：2008-12-23
申请号：US11531398
申请日：2006-09-13
申请人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
发明人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.
摘要翻译：在由多个宏功能逻辑块组成的分层半导体数字单元中，每个所述宏功能逻辑块由多个叶单元组成，每个所述叶单元经由输入端和输出端访问，其中定位每个输入终端提供对靠近输入终端提供访问的叶单元的合法位置处的单个叶单元的访问。

2. 发明授权

US07809874B2 Method for resource sharing in a multiple pipeline environment 有权
标题翻译：多管道环境中资源共享的方法
公开(公告)号：US07809874B2
公开(公告)日：2010-10-05
申请号：US11425398
申请日：2006-06-21
申请人： Patrick J. Meaney , Michael Fee , Christopher M. Carney
发明人： Patrick J. Meaney , Michael Fee , Christopher M. Carney
IPC分类号： G06F13/14
CPC分类号： G06F13/37
摘要： Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is the concept of retry tags for better priority to avoid lock-out. The system also includes round-robin tokens to manage rejected requests to allow better fairness on conflicts. While the processing logic employed specifically applies to cross-interrogation, the logic can be extended to other common resources. The illustrated SMP computer system also has self-correcting logic to maintain good round-robin tokens.
摘要翻译：公开了一种用于通过SMP计算机系统的共享资源在多个管线之间仲裁的方法和装置。该计算机包括延迟仲裁的逻辑，直到稍后的管道，以帮助减少每个管道的延迟。此外，引入了重试标签的概念，以便更好地优先避免锁定。该系统还包括循环令牌来管理被拒绝的请求，以使冲突更加公平。虽然采用的处理逻辑特别适用于交叉询问，但逻辑可以扩展到其他公共资源。所示的SMP计算机系统还具有自校正逻辑，以保持良好的循环令牌。

3. 发明申请

US20080066039A1 Semi-Flattened Pin Optimization Process for Hierarchical Physical Designs 失效
标题翻译：用于分层物理设计的半平面针优化过程
公开(公告)号：US20080066039A1
公开(公告)日：2008-03-13
申请号：US11531398
申请日：2006-09-13
申请人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
发明人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access
摘要翻译：在由多个宏功能逻辑块组成的分层半导体数字单元中，每个所述宏功能逻辑块由多个叶单元组成，每个所述叶单元经由输入端和输出端访问，其中定位每个输入终端提供对靠近输入终端提供访问的叶单元的合法位置处的单个叶单元的访问

4. 发明授权

US07752585B2 Method, apparatus, and computer program product for stale NDR detection 有权
标题翻译：用于陈旧NDR检测的方法，设备和计算机程序产品
公开(公告)号：US07752585B2
公开(公告)日：2010-07-06
申请号：US11872183
申请日：2007-10-15
申请人： Christopher M. Carney , Vern A. Victoria
发明人： Christopher M. Carney , Vern A. Victoria
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： Best and most recent NDR types are selected for all RLM's in a design in order to achieve timing closure. The selection employed uses two levels of filtering to examine the NDR types for each RLM, and based on the outcome of the filtering selects the most appropriate NDR type for input to the timing analysis. In one arrangement, the selection scheme is completely automated and is performed at the beginning of a timing analysis via script-driven processes.
摘要翻译：为了实现定时关闭，所有RLM的设计都选择了最佳和最新的NDR类型。所采用的选择使用两个级别的过滤来检查每个RLM的NDR类型，并且基于过滤的结果选择用于输入到时序分析的最适合的NDR类型。在一种布置中，选择方案是完全自动化的，并且通过脚本驱动的过程在时序分析开始时执行。

5. 发明申请

US20090100395A1 Method, Apparatus, and Computer Program Product for Stale NDR Detection 有权
标题翻译：用于陈旧NDR检测的方法，仪器和计算机程序产品
公开(公告)号：US20090100395A1
公开(公告)日：2009-04-16
申请号：US11872183
申请日：2007-10-15
申请人： Christopher M. Carney , Vern A. Victoria
发明人： Christopher M. Carney , Vern A. Victoria
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： Best and most recent NDR types are selected for all RLM's in a design in order to achieve timing closure. The selection employed uses two levels of filtering to examine the NDR types for each RLM, and based on the outcome of the filtering selects the most appropriate NDR type for input to the timing analysis. In one arrangement, the selection scheme is completely automated and is performed at the beginning of a timing analysis via script-driven processes.
摘要翻译：为了实现定时关闭，所有RLM的设计都选择了最佳和最新的NDR类型。所采用的选择使用两个级别的过滤来检查每个RLM的NDR类型，并且基于过滤的结果选择用于输入到时序分析的最适合的NDR类型。在一种布置中，选择方案是完全自动化的，并且通过脚本驱动的过程在时序分析开始时执行。

6. 发明授权

US07480886B2 VLSI timing optimization with interleaved buffer insertion and wire sizing stages 失效
标题翻译：具有交错缓冲器插入和线尺寸阶段的VLSI时序优化
公开(公告)号：US07480886B2
公开(公告)日：2009-01-20
申请号：US11334256
申请日：2006-01-18
申请人： Christopher M. Carney , Vern A. Victoria
发明人： Christopher M. Carney , Vern A. Victoria
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5068
摘要： The invention relates to layout of circuit components, including determining the interconnections, buffers, or path nets between circuit blocks or circuit components and input/output bonding pads. This is accomplished by a method and program product that optimizes timing comprising. Wiring layout and buffer insertion is accomplished by setting all wires in the design to an initial best possible value, inserting buffers in longest nets of wires of the design, and degrading the resulting nets. This is accomplished by a wire sizing routine which takes the nets and degrades them accordingly. This degrading is done through a combination of one or more of knocking the wires down to lower levels and reducing their thickness. The amount of degradation is dependent on the final slack.
摘要翻译：本发明涉及电路组件的布局，包括确定电路块或电路组件之间的互连，缓冲器或路径网以及输入/输出接合焊盘。这是通过一种优化时序的方法和程序产品实现的，包括。布线布局和缓冲区插入是通过将设计中的所有导线设置为初始的最佳可能值来实现的，将缓冲区插入设计中最长的网线，并降低所得的网络。这是通过线网规则实现的，该规则采取网络并相应地降低它们。这种降级是通过一种或多种将电线敲低到较低水平并减小其厚度的组合而完成的。退化的量取决于最后的松弛。

7. 发明申请

US20070300040A1 Method for Resource Sharing in a Multiple Pipeline Environment 有权
标题翻译：多管道环境资源共享方法
公开(公告)号：US20070300040A1
公开(公告)日：2007-12-27
申请号：US11425398
申请日：2006-06-21
申请人： Patrick J. Meaney , Michael Fee , Christopher M. Carney
发明人： Patrick J. Meaney , Michael Fee , Christopher M. Carney
IPC分类号： G06F15/00 , G06F13/14
CPC分类号： G06F13/37
摘要： Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is the concept of retry tags for better priority to avoid lock-out. The system also includes round-robin tokens to manage rejected requests to allow better fairness on conflicts. While the processing logic employed specifically applies to cross-interrogation, the logic can be extended to other common resources. The illustrated SMP computer system also has self-correcting logic to maintain good round-robin tokens.
摘要翻译：公开了一种用于通过SMP计算机系统的共享资源在多个管线之间仲裁的方法和装置。该计算机包括延迟仲裁的逻辑，直到稍后的管道，以帮助减少每个管道的延迟。此外，引入了重试标签的概念，以便更好地优先避免锁定。该系统还包括循环令牌来管理被拒绝的请求，以使冲突更加公平。虽然采用的处理逻辑特别适用于交叉询问，但逻辑可以扩展到其他公共资源。所示的SMP计算机系统还具有自校正逻辑，以保持良好的循环令牌。

8. 发明授权

US07882472B2 Method, apparatus, and computer program product for automatically waiving non-compute indications for a timing analysis process 有权
标题翻译：方法，装置和计算机程序产品，用于自动放弃计时分析过程的非计算指示
公开(公告)号：US07882472B2
公开(公告)日：2011-02-01
申请号：US11871179
申请日：2007-10-12
申请人： Nicholas P. Sardino , Sean M. Carey , Christopher M. Carney , Vern Anthony Victoria
发明人： Nicholas P. Sardino , Sean M. Carey , Christopher M. Carney , Vern Anthony Victoria
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test for a given phase at a test point. A process automatically verifies that all non-computes are understood and exist for valid reasons, in order to ensure all necessary paths are being timed. The process takes a conventional Comprehensive Report output of a unit timing run and generates macro specific N/C reports for designers to review and sign off on.
摘要翻译：在单元定时过程中，存在在IC芯片设计中的特定网络上的非计算（N / C）的可能性，其可能由许多事情引起，包括但不限于引脚被绑定到电源，浮动输出或在测试点的给定阶段的无效时序测试。过程会自动验证所有非计算机是否被理解并存在，以确保所有必需的路径都被计时。该过程采用单位计时运行的常规综合报告输出，并为设计人员生成宏观特定的N / C报告进行审查和签名。

9. 发明申请

US20090100394A1 Method, Apparatus, and Computer Program Product for Automatically Waiving Non-Compute Indications for a Timing Analysis Process 有权
标题翻译：方法，设备和计算机程序产品，用于自动放弃用于定时分析过程的非计算指示
公开(公告)号：US20090100394A1
公开(公告)日：2009-04-16
申请号：US11871179
申请日：2007-10-12
申请人： Nicholas P. Sardino , Sean M. Carey , Christopher M. Carney , Vern Anthony Victoria
发明人： Nicholas P. Sardino , Sean M. Carey , Christopher M. Carney , Vern Anthony Victoria
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test for a given phase at a test point. A process automatically verifies that all non-computes are understood and exist for valid reasons, in order to ensure all necessary paths are being timed. The process takes a conventional Comprehensive Report output of a unit timing run and generates macro specific N/C reports for designers to review and sign off on.
摘要翻译：在单元定时过程中，存在在IC芯片设计中的特定网络上的非计算（N / C）的可能性，其可能由许多事情引起，包括但不限于引脚被绑定到电源，浮动输出或在测试点的给定阶段的无效时序测试。过程会自动验证所有非计算机是否被理解并存在，以确保所有必需的路径都被计时。该过程采用单位计时运行的常规综合报告输出，并为设计人员生成宏观特定的N / C报告进行审查和签名。

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