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1. 发明授权

US07915027B2 Surfactant biocatalyst for remediation of recalcitrant organics and heavy metals 有权
标题翻译：用于修复顽抗性有机物和重金属的表面活性剂生物催化剂
公开(公告)号：US07915027B2
公开(公告)日：2011-03-29
申请号：US11810731
申请日：2007-06-07
申请人： Robin L. Brigmon , Sandra Story , Denis J. Altman , Christopher J. Berry
发明人： Robin L. Brigmon , Sandra Story , Denis J. Altman , Christopher J. Berry
IPC分类号： A62D3/00 , A62D3/02 , B09B3/00 , B09C1/10 , C10G32/00 , D06M16/00
CPC分类号： B09C1/10 , C12R1/01 , C12R1/05 , C12R1/40 , C12R1/41 , C12R1/425 , C12R1/44 , G21F9/18 , G21F9/28 , Y10S435/829 , Y10S435/874 , Y10S435/877 , Y10S435/878 , Y10S435/88 , Y10S435/882
摘要： Novel strains of isolated and purified bacteria have been identified which have the ability to degrade petroleum hydrocarbons including a variety of PAHs. Several isolates also exhibit the ability to produce a biosurfactant. The combination of the biosurfactant-producing ability along with the ability to degrade PAHs enhances the efficiency with which PAHs may be degraded. Additionally, the biosurfactant also provides an additional ability to bind heavy metal ions for removal from a soil or aquatic environment.
摘要翻译：已经鉴定了具有分解和纯化的细菌的新菌株，其具有降解包括各种多环芳烃在内的石油烃的能力。几种分离物也表现出生产生物表面活性剂的能力。生物表面活性剂生产能力的组合以及降解PAHs的能力提高了多环芳烃降解的效率。此外，生物表面活性剂还提供了结合重金属离子以从土壤或水生环境中去除的附加能力。

2. 发明授权

US07859116B1 Exposed metal bezel for use in sensor devices and method therefor 有权
标题翻译：用于传感器装置的暴露的金属表圈及其方法
公开(公告)号：US07859116B1
公开(公告)日：2010-12-28
申请号：US11616069
申请日：2006-12-26
申请人： Michael G. Kelly , Christopher J. Berry , Christopher M. Scanlan
发明人： Michael G. Kelly , Christopher J. Berry , Christopher M. Scanlan
IPC分类号： H01L23/48
CPC分类号： G06K9/00053 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/48227 , H01L2224/49171 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A sensor package has a substrate. A sensor die having an inactive surface is bonded to the substrate. An active surface of the sensor die is exposed. A portion of the active surface of the sensor die has an active imaging area. A metal bezel is formed on the active surface of the sensor die and separate from the imaging area.
摘要翻译：传感器封装具有基板。具有非活性表面的传感器芯片被结合到基板上。传感器裸片的活性表面露出。传感器管芯的有效表面的一部分具有主动成像区域。在传感器芯片的有源表面上形成金属边框，并与成像区域分离。

3. 发明授权

US07687899B1 Dual laminate package structure with embedded elements 有权
标题翻译：双层压封装结构，嵌入式元件
公开(公告)号：US07687899B1
公开(公告)日：2010-03-30
申请号：US11835235
申请日：2007-08-07
申请人： Christopher J. Berry
发明人： Christopher J. Berry
IPC分类号： H01L23/22
CPC分类号： H01L21/561 , H01L23/3121 , H01L23/5385 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32013 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1041 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/3025 , H01L2924/00 , H01L2224/32145 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An interconnect structure (i.e., an interposer) which is mounted and electrically connected to a bottom semiconductor package substrate either prior or subsequent to such bottom substrate being populate with one or more electronic components. Subsequently, a top semiconductor package substrate which may also be populated with one or more electronic components is mounted to the interposer, such that all of the electronic components are disposed between the top and bottom interposers. Thereafter, a suitable mold compound is injected between the top and bottom substrates, the mold compound flowing about the electronic components, between the BGA joints, and at least partially about the interposer, thus helping to lock the interposer in place in the completed semiconductor package.
摘要翻译：在这种底部基板之前或之后，安装并电连接到底部半导体封装基板的互连结构（即，插入器）填充有一个或多个电子部件。随后，也可以将一个或多个电子元件的顶部半导体封装基板安装到插入器上，使得所有电子部件都设置在顶部和底部插入件之间。此后，在顶部和底部基底之间注射合适的模制化合物，模制化合物围绕电子部件流动，在BGA接头之间，并且至少部分地围绕插入件，从而有助于将插入件锁定在完成的半导体封装中的适当位置。

4. 发明申请

US20080263493A1 Method and Apparatus for Tie Net Routing 审中-公开
标题翻译：铁网路由方法与装置
公开(公告)号：US20080263493A1
公开(公告)日：2008-10-23
申请号：US11737280
申请日：2007-04-19
申请人： Christopher J Berry , Alan Wagstaff
发明人： Christopher J Berry , Alan Wagstaff
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/78
摘要： A method of performing tie net routing within an integrated circuit chip is disclosed without using wiring. Due to repeated use of designs in modern chip, there are often unused portions of the design that need to be connected permanently to a local logical1 or logical 0. These connections, known as tie nets, are not timing critical signals that, when poorly implemented can get in the way of functional signals in an integrated circuit. The current method is to connect the pin to the nearest power connections of the correct polarity. This requires some amount of wiring resources that may be needed for other functions or pin access. Accordingly, the present invention avoids this situation by avoiding wiring.
摘要翻译：在不使用布线的情况下公开了在集成电路芯片内执行连接网路由的方法。由于在现代芯片中重复使用设计，通常设计中未使用的部分需要永久连接到本地逻辑1或逻辑0。这些连接称为连接网络不是时序关键信号，当执行不良时可以阻碍集成电路中的功能信号。目前的方法是将引脚连接到正确极性的最近的电源连接。这需要一些其他功能或引脚访问可能需要的接线资源。因此，本发明通过避免布线来避免这种情况。

5. 发明申请

US20080066039A1 Semi-Flattened Pin Optimization Process for Hierarchical Physical Designs 失效
标题翻译：用于分层物理设计的半平面针优化过程
公开(公告)号：US20080066039A1
公开(公告)日：2008-03-13
申请号：US11531398
申请日：2006-09-13
申请人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
发明人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access
摘要翻译：在由多个宏功能逻辑块组成的分层半导体数字单元中，每个所述宏功能逻辑块由多个叶单元组成，每个所述叶单元经由输入端和输出端访问，其中定位每个输入终端提供对靠近输入终端提供访问的叶单元的合法位置处的单个叶单元的访问

6. 发明授权

US07342303B1 Semiconductor device having RF shielding and method therefor 有权
标题翻译：具有RF屏蔽的半导体器件及其方法
公开(公告)号：US07342303B1
公开(公告)日：2008-03-11
申请号：US11364427
申请日：2006-02-28
申请人： Christopher J. Berry , Christopher M. Scanlan
发明人： Christopher J. Berry , Christopher M. Scanlan
IPC分类号： H01L23/00
CPC分类号： H01L23/552 , H01L23/13 , H01L23/29 , H01L23/3128 , H01L23/5389 , H01L24/48 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/81801 , H01L2224/83 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15159 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/3025 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device and method of manufacturing has a substrate having a plurality of metal layers. At least one metal layer is exposed on at least one side surface of the semiconductor device. A die is coupled to the substrate. A mold compound encapsulates the die and a top surface of the substrate. A conductive coating is applied to the mold compound and to at least one metal layer exposed on at least one side surface of the substrate.
摘要翻译：半导体器件和制造方法具有具有多个金属层的衬底。至少一个金属层暴露在半导体器件的至少一个侧面上。模具耦合到基板。模具化合物封装模具和衬底的顶表面。将导电涂层施加到模制化合物和暴露于基底的至少一个侧表面上的至少一个金属层。

7. 发明申请

US20080059952A1 Method for Replicating and Synchronizing a Plurality of Physical Instances with a Logical Master 失效
标题翻译：使用逻辑主机复制和同步多个物理实例的方法
公开(公告)号：US20080059952A1
公开(公告)日：2008-03-06
申请号：US11468031
申请日：2006-08-29
申请人： Gary A. Van Huben , David A. Webber , Christopher J. Berry
发明人： Gary A. Van Huben , David A. Webber , Christopher J. Berry
IPC分类号： G06F9/44
CPC分类号： G06F17/30575 , G06F11/2094
摘要： Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set, Design Data Management employs replicating common data sets into one or more clone data sets. The method preferred provides for replicating and synchronizing one or more data sets with a master data set, comprises providing data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances to enable customization of said one or more physical instances. The master data set describes at least one of: a design component, a circuit macro, and a circuit entity, and comprises logical data sets, and it comprise physical design data sets. This permits all existing verification processes that are normally executed against the common data set to also be equally applied to the clones of said data set by way of automatic synchronization between of the common dataset and the clones.
摘要翻译：设计数据管理使用一个共同的数据集副本以及多个实例，同时继续利用现有的设计数据库和现有的CAD工具。允许最小量的用户干预来创建和维护公共数据集，设计数据管理使用将一般数据集复制到一个或多个克隆数据集中。该方法优选地提供用于复制和同步一个或多个数据集与主数据集，包括提供主数据集和至少一个克隆数据集的数据设计管理，以及将主物理设计数据集复制到一个或多个物理允许定制所述一个或多个物理实例的实例。主数据集描述了设计组件，电路宏和电路实体中的至少一个，并且包括逻辑数据集，并且它包括物理设计数据集。这允许通常针对公共数据集执行的所有现有验证过程也可以通过公共数据集和克隆之间的自动同步同样地应用于所述数据集的克隆。

8. 发明授权

US07269806B2 Decoupling capacitance analysis method 失效
标题翻译：去耦电容分析方法
公开(公告)号：US07269806B2
公开(公告)日：2007-09-11
申请号：US11408228
申请日：2006-04-20
申请人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
发明人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.
摘要翻译：用于去耦电容分析的这种方法改进了现有技术，以试图给出对芯片上的电源波动的更准确的表示，同时保持运行时可比性。该方法采用以下技术; a）通过层级降级并将设计划分为可变尺寸网格的方法; b）确定设计的哪些网格位置对于该网格位置中的所有设备没有足够的去耦电容器的算法; c）确定哪些网格位置受到有害的相邻影响的算法; 以及d）以图形方式显示计算结果的方法，以便容易地识别问题区域。

9. 发明授权

US07086026B2 Decoupling capacitance analysis method 失效
标题翻译：去耦电容分析方法
公开(公告)号：US07086026B2
公开(公告)日：2006-08-01
申请号：US10436393
申请日：2003-05-12
申请人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
发明人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques: 1. A method for descending through hierarchy and dividing the design into a variable sized grid. 2. An algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location. 3. An algorithm to determine which grid locations are subject to harmful neighboring effects. 4. A method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.
摘要翻译：用于去耦电容分析的这种方法改进了现有技术，以试图给出对芯片上的电源波动的更准确的表示，同时保持运行时可比性。该方法采用以下技术：1.一种通过层级降级并将设计划分为可变尺寸网格的方法。 2.一种用于确定设计的哪些网格位置对于该网格位置中的所有设备没有足够的去耦电容的算法。 3.确定哪些网格位置受到有害的相邻影响的算法。 4.以图形方式显示计算结果的方法，以便轻松识别问题区域。

10. 发明授权

US08319338B1 Thin stacked interposer package 有权
标题翻译：薄堆叠插入器封装
公开(公告)号：US08319338B1
公开(公告)日：2012-11-27
申请号：US12832202
申请日：2010-07-08
申请人： Christopher J. Berry , Christopher M. Scanlan
发明人： Christopher J. Berry , Christopher M. Scanlan
IPC分类号： H01L23/48
CPC分类号： H01L23/3128 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/06517 , H01L2225/06541 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/078 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： The present invention comprises a semiconductor package comprising a bottom semiconductor package substrate which is populated with one or more electronic components. The electronic component(s) of the bottom substrate are covered or encapsulated with a suitable mold compound which hardens into a package body of the semiconductor package. The package body is provided with one or more vias through the completion of laser drilling process, such via(s) providing access to one or more corresponding conductive contacts of the bottom substrate. These vias are either lined or partially filled with a conductive metal material. Subsequently, a top semiconductor package substrate (which may optionally be populated with one or more electronic components) is mounted to the package body and electrically connected to the conductive metal within the via(s) of the package body.
摘要翻译：本发明包括一个半导体封装，它包括一个底部的半导体封装衬底，其中填充有一个或多个电子元件。底部基板的电子部件被适当的模制化合物覆盖或封装，所述合适的模制化合物硬化到半导体封装的封装主体中。通过完成激光钻孔工艺，该封装主体设置有一个或多个通孔，这样的通孔提供对底部基板的一个或多个对应的导电触点的通路。这些通孔用导电金属材料衬里或部分填充。随后，将顶部半导体封装衬底（其可选地填充有一个或多个电子部件）安装到封装主体并电连接到封装主体的通孔内的导电金属。

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