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1. 发明授权

US09672153B2 Memory interface control 有权
公开(公告)号：US09672153B2
公开(公告)日：2017-06-06
申请号：US13067602
申请日：2011-06-13
申请人： Christopher William Laycock , Antony John Harris , Arthur Laughton
发明人： Christopher William Laycock , Antony John Harris , Arthur Laughton
IPC分类号： G06F12/00 , G06F12/0831
CPC分类号： G06F12/0835 , G06F12/0831 , G06F12/0833
摘要： A memory interface apparatus 24 is provided with first interface circuitry 28, second interface circuitry 30 and transaction control circuitry 32. The first interface circuitry receives a first write request from a transaction master 20, 22 and issues a further transaction request associated with the memory address of the first write request via the second interface circuitry to a memory system. When an indication of the completion of the further transaction has been received at the second interface circuitry, then a second write request may be issued from the second interface circuitry to the memory system to write the target data associated with the first write request. After a write response signal in respect of the second write request is received at the second interface circuitry, then an acknowledge signal RACK indicating completion of the further transaction and that the write response signal has been received may be issued from the second interface circuitry. Between issue of the further transaction and issue of the acknowledge signal snoop requests to the memory addresses concerned that arise elsewhere within the memory system may be managed and blocked.

2. 发明授权

US08856408B2 Reduced latency barrier transaction requests in interconnects 有权
标题翻译：减少互连中的延迟屏障事务请求
公开(公告)号：US08856408B2
公开(公告)日：2014-10-07
申请号：US12923723
申请日：2010-10-05
申请人： Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
发明人： Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
IPC分类号： G06F3/00 , G06F5/00 , G06F13/362 , G06F13/364 , G06F13/16
CPC分类号： G06F13/362 , G06F13/1621 , G06F13/1689 , G06F13/364
摘要： Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the circuitry including at least one input for receiving transaction requests; at least one output for outputting transaction requests; at least one path for transmitting the transaction requests between the input and the output. Control circuitry routes received transaction requests from the input to the output in response to a barrier transaction request. An ordering of at least some transaction requests is maintained with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests. The control circuitry includes a response signal generator, the response signal generator is responsive to receipt of the barrier transaction request to issue a response signal.
摘要翻译：互连电路被配置为提供数据路由，至少一个发起者设备可经由该路径访问至少一个接收方设备，该电路包括用于接收交易请求的至少一个输入; 用于输出交易请求的至少一个输出; 用于在输入和输出之间传送事务请求的至少一个路径。响应于屏障事务请求，控制电路将接收的事务请求从输入路由到输出。通过不允许对至少一些交易请求进行重新排序，关于通过所述至少一个路径中的一个路径的事务请求流中的屏障事务请求来维护至少一些事务请求的排序。控制电路包括响应信号发生器，响应信号发生器响应于接收到屏障事务请求以发出响应信号。

3. 发明申请

US20090319707A1 Control of master/slave communication within an integrated circuit 有权
标题翻译：控制集成电路内的主/从通讯
公开(公告)号：US20090319707A1
公开(公告)日：2009-12-24
申请号：US12213470
申请日：2008-06-19
申请人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Richard Roy Grisenthwaite , Stuart David Biles
发明人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Richard Roy Grisenthwaite , Stuart David Biles
IPC分类号： G06F13/40
CPC分类号： G06F13/4221
摘要： An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.
摘要翻译：集成电路2包括经由互连电路10连接到交易从属单元12的交易主机4.交易从机12产生传输完成信号（R Last或B）以指示完成数据传送（读或写）。当该传输完成信号已被交易主机4接收到时，交易主机4产生一个完整确认信号RACK，其返回到交易从属单元，以便确认传送完成信号的接收。

4. 发明申请

US20110087819A1 Barrier transactions in interconnects 有权
标题翻译：互连中的障碍事务
公开(公告)号：US20110087819A1
公开(公告)日：2011-04-14
申请号：US12923727
申请日：2010-10-05
申请人： Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
发明人： Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
IPC分类号： G06F13/14
CPC分类号： G06F13/362 , G06F13/1621 , G06F13/1689 , G06F13/364
摘要： Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to said at least one recipient device; at least one path for transmitting said transaction requests between said at least one input and said at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after said bather transaction request in said stream of transaction requests; wherein said bather transaction request comprising an indicator indicating which of said transaction requests within said stream of transaction requests comprise said at least some transaction requests whose ordering is to be maintained.
摘要翻译：公开了一种用于数据处理装置的互连电路。所述互连电路被配置为提供数据路由，至少一个发起者设备可经由该路径访问至少一个接收方设备，所述互连电路包括：用于从所述至少一个启动器设备接收事务请求的至少一个输入; 用于向所述至少一个接收设备输出交易请求的至少一个输出; 用于在所述至少一个输入和所述至少一个输出之间传送所述事务请求的至少一个路径; 用于将所述接收的交易请求从所述至少一个输入路由到所述至少一个输出的控制电路; 其中所述控制电路被配置为响应于屏障事务请求，以通过不允许重新排序来保持在通过所述至少一个路径之一的事务请求流内关于所述屏障事务请求的至少一些事务请求的排序在所述事务请求流中的所述屏障事务请求之前发生的至少一些事务请求相对于在所述事务请求流中的所述沐浴事务请求之后发生的至少一些事务请求; 其中所述沐浴事务请求包括指示所述事务请求流内的所述事务请求中的哪一个包括所述至少一些其顺序要保持的事务请求的指示符。

5. 发明授权

US07757027B2 Control of master/slave communication within an integrated circuit 有权
标题翻译：控制集成电路内的主/从通讯
公开(公告)号：US07757027B2
公开(公告)日：2010-07-13
申请号：US12213470
申请日：2008-06-19
申请人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Richard Roy Grisenthwaite , Stuart David Biles
发明人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Richard Roy Grisenthwaite , Stuart David Biles
IPC分类号： G06F13/00
CPC分类号： G06F13/4221
摘要： An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.
摘要翻译：集成电路2包括经由互连电路10连接到交易从属单元12的交易主机4.交易从机12产生传输完成信号（R Last或B）以指示完成数据传送（读或写）。当该传输完成信号已被交易主机4接收到时，交易主机4产生一个完整确认信号RACK，其返回到交易从属单元，以便确认传送完成信号的接收。

6. 发明授权

US08732400B2 Data store maintenance requests in interconnects 有权
标题翻译：互连中的数据存储维护请求
公开(公告)号：US08732400B2
公开(公告)日：2014-05-20
申请号：US12923725
申请日：2010-10-05
申请人： Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
发明人： Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
IPC分类号： G06F12/00
CPC分类号： G06F13/362 , G06F13/1621 , G06F13/1689 , G06F13/364
摘要： Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The interconnect circuitry comprises: at least one input for receiving transaction requests from the initiator device(s); at least one output for outputting transaction requests to the recipient device(s); a plurality of paths for transmitting said transaction requests between the at least one input and the at least one output; wherein at least one of said transaction requests comprises a data store maintenance request requesting a data store maintenance operation to be performed on data stores within the data processing apparatus; and control circuitry for routing the received transaction requests from the at least one input to the at least one output; wherein the control circuitry is configured to respond to receipt of the data store maintenance operation by transmitting the data store maintenance operation along at least one of the plurality of paths followed by a barrier transaction request, the control circuitry being configured to maintain an ordering of at least some transaction requests with respect to the barrier transaction request within a stream of transaction requests passing along the at least one of said plurality of paths, such that at least some transaction requests subsequent to the data store maintenance request in the stream of transaction requests are held behind the data store maintenance request by the barrier transaction request.
摘要翻译：公开了一种用于数据处理装置的互连电路。互连电路被配置为提供数据路由，至少一个发起者设备可经由该路由访问至少一个接收者设备。所述互连电路包括：用于接收来自所述发起者设备的交易请求的至少一个输入; 至少一个用于向所述接收方设备输出交易请求的输出; 用于在所述至少一个输入和所述至少一个输出之间传送所述事务请求的多条路径; 其中所述交易请求中的至少一个包括数据存储维护请求，请求在所述数据处理设备内的数据存储器上执行数据存储维护操作; 以及用于将所接收的交易请求从所述至少一个输入路由到所述至少一个输出的控制电路; 其中所述控制电路被配置为通过沿着所述多个路径中的至少一个路径发送所述数据存储维护操作来响应于所述数据存储维护操作的接收，所述控制电路被配置为维持在在沿所述多个路径中的至少一个路径传递的事务请求流内的至少一些关于屏障事务请求的事务请求，使得在事务请求流中的数据存储维护请求之后的至少一些事务请求是通过屏障事务请求在数据存储维护请求之后。

7. 发明授权

US08589631B2 Coherency control with writeback ordering 有权
标题翻译：具有回写排序的一致性控制
公开(公告)号：US08589631B2
公开(公告)日：2013-11-19
申请号：US13137780
申请日：2011-09-12
申请人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Stuart David Biles
发明人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Stuart David Biles
IPC分类号： G06F12/00
CPC分类号： G06F12/0833 , Y02D10/13
摘要： Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.
摘要翻译：互连电路，被配置为提供用于互连多个发起者设备和至少一个包括存储器的接收设备的路由。至少一个启动器设备具有用于存储存储在存储器中的数据项的子集的本地副本的高速缓存。所述互连电路包括：多个输入端口和至少一个输出端口; 用于在所述输入和所述至少一个输出之间传送交易请求的多个路径; 一致性控制电路，用于维持其中至少一些交易请求到同一数据存储位置的顺序通过互连电路进行。互连电路被配置为不利用一致性控制电路控制回写事务请求，使得回写事务请求独立于通过一致性控制电路路由的事务请求而进行。

8. 发明申请

US20120317368A1 Memory interface control 有权
标题翻译：存储器接口控制
公开(公告)号：US20120317368A1
公开(公告)日：2012-12-13
申请号：US13067602
申请日：2011-06-13
申请人： Christopher William Laycock , Antony John Harris , Arthur Laughton
发明人： Christopher William Laycock , Antony John Harris , Arthur Laughton
IPC分类号： G06F12/08
CPC分类号： G06F12/0835 , G06F12/0831 , G06F12/0833
摘要： A memory interface apparatus 24 is provided with first interface circuitry 28, second interface circuitry 30 and transaction control circuitry 32. The first interface circuitry receives a first write request from a transaction master 20, 22 and issues a further transaction request associated with the memory address of the first write request via the second interface circuitry to a memory system. When an indication of the completion of the further transaction has been received at the second interface circuitry, then a second write request may be issued from the second interface circuitry to the memory system to write the target data associated with the first write request. After a write response signal in respect of the second write request is received at the second interface circuitry, then an acknowledge signal RACK indicating completion of the further transaction and that the write response signal has been received may be issued from the second interface circuitry. Between issue of the further transaction and issue of the acknowledge signal snoop requests to the memory addresses concerned that arise elsewhere within the memory system may be managed and blocked.
摘要翻译：存储器接口装置24设置有第一接口电路28，第二接口电路30和事务控制电路32.第一接口电路从事务主机20,22接收第一写入请求，并且发出与存储器地址相关联的另外的事务请求的第一写入请求经由第二接口电路传送到存储器系统。当在第二接口电路处接收到进一步交易的完成的指示时，则可以从第二接口电路向存储器系统发出第二写入请求，以写入与第一写入请求相关联的目标数据。在第二接口电路上接收到关于第二写入请求的写入响应信号之后，可以从第二接口电路发出指示进一步事务的完成的确认信号RACK和已经接收到写入响应信号。在进一步交易的发行和对存储器系统中其他地方出现的相关存储器地址的确认信号窥探请求的发出之间可能被管理和阻止。

9. 发明申请

US20120079211A1 Coherency control with writeback ordering 有权
标题翻译：具有回写排序的一致性控制
公开(公告)号：US20120079211A1
公开(公告)日：2012-03-29
申请号：US13137780
申请日：2011-09-12
申请人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Stuart David Biles
发明人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Stuart David Biles
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , Y02D10/13
摘要： Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.
摘要翻译：互连电路，被配置为提供用于互连多个发起者设备和至少一个包括存储器的接收设备的路由。至少一个启动器设备具有用于存储存储在存储器中的数据项的子集的本地副本的高速缓存。所述互连电路包括：多个输入端口和至少一个输出端口; 用于在所述输入和所述至少一个输出之间传送交易请求的多个路径; 一致性控制电路，用于维持其中至少一些交易请求到同一数据存储位置的顺序通过互连电路进行。互连电路被配置为不利用一致性控制电路控制回写事务请求，使得回写事务请求独立于通过一致性控制电路路由的事务请求而进行。

10. 发明申请

US20110125944A1 Synchronising activities of various components in a distributed system 有权
标题翻译：在分布式系统中同步各种组件的活动
公开(公告)号：US20110125944A1
公开(公告)日：2011-05-26
申请号：US12923906
申请日：2010-10-13
申请人： Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
发明人： Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F13/1621 , G06F13/1689 , G06F13/364
摘要： An initiator device for issuing transaction requests to a recipient device via an interconnect is disclosed. The initiator device comprises: at least one port for receiving requests from and issuing requests to said interconnect; a barrier generator for generating barrier transaction requests, the barrier transaction requests indicating to the interconnect that an ordering of at least some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of at least some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request; wherein in response to receipt of a synchronise request querying progress of at least a subset of transaction requests, the initiator device is responsive to action any pending transaction requests within the at least a subset of transaction request and to generate a barrier transaction request at the barrier generator and to issue the barrier transaction request to the interconnect via the at least one port, and in response to receiving a response to the barrier transaction request to issue an acknowledge signal as a response to the synchronise request.
摘要翻译：公开了一种用于经由互连向接收方设备发出交易请求的发起者设备。所述发起者设备包括：用于从所述互连接收请求并向所述互连发出请求的至少一个端口; 用于产生屏障事务请求的屏障发生器，所述屏障事务请求向所述互连指示通过所述互连的事务请求流内的至少一些事务请求的排序应该通过不允许重新排序所述事务中的至少一些来维持关于屏障交易请求的交易请求流中的屏障事务请求之前发生的请求; 其中响应于接收到查询至少一个事务请求的子集的进程的同步请求，所述发起者设备响应于所述事务请求的所述至少一个子集内的任何待处理的事务请求的动作，并在所述屏障上生成屏障事务请求并且经由至少一个端口向互连发出屏障事务请求，并且响应于接收到对屏障事务请求的响应来发出确认信号作为对同步请求的响应。

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