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1. 发明申请

US20140052921A1 STORE-EXCLUSIVE INSTRUCTION CONFLICT RESOLUTION 有权
标题翻译：存储专用指令冲突解决方案
公开(公告)号：US20140052921A1
公开(公告)日：2014-02-20
申请号：US14113723
申请日：2012-05-21
申请人： Stuart David Biles , Richard Roy Grisenthwaite , Bruce James Mathewson
发明人： Stuart David Biles , Richard Roy Grisenthwaite , Bruce James Mathewson
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F9/3004 , G06F9/3834 , G06F12/0815 , G06F12/0817
摘要： A data processing system includes a plurality of transaction masters (4, 6, 8, 10) each with an associated local cache memory (12, 14, 16, 18) and coupled to coherent interconnect circuitry (20). Monitoring circuitry (24) within the coherent interconnect circuitry (20) maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.
摘要翻译：数据处理系统包括多个具有相关本地高速缓存存储器（12,14,16,18）并且耦合到相干互连电路（20）的交易主机（4,6,8,10）。相干互连电路（20）内的监控电路（24）维护关于每个交易主机的状态变量（标志），以监视该交易主机的独占存储访问状态是否正在等待。当事务主机要执行存储专用指令时，将该事务主机的主体状态变量的当前值与设置独占存储访问时存储的该变量的先前值进行比较。如果存在匹配，则允许存储专用指令继续进行，并且具有挂起的独占存储访问状态的所有其他事务主器件的状态变量被改变。如果没有匹配，则专用指令的执行被标记为失败。

2. 发明授权

US08375170B2 Apparatus and method for handling data in a cache 有权
标题翻译：用于处理缓存中的数据的装置和方法
公开(公告)号：US08375170B2
公开(公告)日：2013-02-12
申请号：US12656709
申请日：2010-02-12
申请人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Andrew Christopher Rose , Richard Roy Grisenthwaite
发明人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Andrew Christopher Rose , Richard Roy Grisenthwaite
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0815 , G06F2212/507 , Y02D10/13
摘要： A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache. Such a mechanism causes the refetch of data into the cache to be triggered by the coherency action performed in response to a coherency request from another portion of the coherent cache system, rather than relying on any actions taken by the at least one master device, thereby providing a very flexible and efficient mechanism for reducing cache latency in a coherent cache system.
摘要翻译：用于形成相干高速缓存系统的一部分的数据处理设备包括用于执行数据处理操作的至少一个主设备和耦合到该至少一个主设备的高速缓存，并且被配置为存储由该至少一个主站访问的数据值设备执行数据处理操作。高速缓存一致性电路响应来自相干高速缓存系统的另一部分的一致性请求，以引起关于存储在高速缓存中的至少一个数据值的一致性动作。响应于一致性动作导致高速缓存中至少一个数据值无效的指示，使用重新读取控制电路来发起将该至少一个数据值重新读取到高速缓存中。这种机制导致数据重新取入缓存以由响应于来自相干高速缓存系统的另一部分的一致性请求而执行的一致性动作来触发，而不是依赖于由至少一个主设备采取的任何动作，从而提供了一种非常灵活和有效的机制来减少一致的缓存系统中的缓存延迟。

3. 发明授权

US08190801B2 Interconnect logic for a data processing apparatus 有权
标题翻译：数据处理设备的互连逻辑
公开(公告)号：US08190801B2
公开(公告)日：2012-05-29
申请号：US11440056
申请日：2006-05-25
申请人： Antony John Harris , Bruce James Mathewson
发明人： Antony John Harris , Bruce James Mathewson
IPC分类号： G06F13/362 , G06F13/14
CPC分类号： G06F13/4027
摘要： Interconnect logic is provided for coupling master logic units and slave logic units within a data processing apparatus to enable transactions to be performed. Each transaction comprises an address transfer from a master logic unit to a slave logic unit and one or more data transfers between that master logic unit and that slave logic unit. The interconnect logic comprises a plurality of connection paths for providing at least one address channel for carrying address transfers and at least one data channel for carrying data transfers, and control logic is used to control the use of the at least one address channel and the at least one data channel in order to enable the transactions to be performed. The control logic comprises address arbiter logic which, for an associated address channel, arbitrates between multiple address transfers seeking to use that associated address channel, and data arbiter logic which, for an associated data channel, arbitrates between multiple data transfers seeking to use that associated data channel. The data arbiter is operable independently of the address arbiter such that the data transfers of multiple transactions can occur out of order with respect to the corresponding address transfers of those multiple transactions. This enables efficient use to be made of the interconnect logic resources.
摘要翻译：互联逻辑被提供用于耦合数据处理设备内的主逻辑单元和从属逻辑单元，以实现交易。每个事务包括从主逻辑单元到从属逻辑单元的地址传送以及该主逻辑单元和该从属逻辑单元之间的一个或多个数据传输。互连逻辑包括用于提供用于承载地址传输的至少一个地址信道和用于承载数据传输的至少一个数据信道的多个连接路径，并且控制逻辑被用于控制至少一个地址信道和at 至少一个数据信道，以便能够执行事务。控制逻辑包括地址仲裁器逻辑，其对于相关联的地址信道，在寻求使用该相关联的地址信道的多个地址传输之间进行仲裁，以及对于相关联的数据信道在寻求使用相关联的地址信道的多个数据传输之间仲裁的数据仲裁器逻辑数据通道。数据仲裁器可以独立于地址仲裁器操作，使得多个事务的数据传输可以相对于那些多个事务的相应地址传送而发生不正常。这使得能够有效地利用互连逻辑资源。

4. 发明申请

US20110202726A1 Apparatus and method for handling data in a cache 有权
标题翻译：用于处理缓存中的数据的装置和方法
公开(公告)号：US20110202726A1
公开(公告)日：2011-08-18
申请号：US12656709
申请日：2010-02-12
申请人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Andrew Christopher Rose , Richard Roy Grisenthwaite
发明人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Andrew Christopher Rose , Richard Roy Grisenthwaite
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0815 , G06F2212/507 , Y02D10/13
摘要： A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache. Such a mechanism causes the refetch of data into the cache to be triggered by the coherency action performed in response to a coherency request from another portion of the coherent cache system, rather than relying on any actions taken by the at least one master device, thereby providing a very flexible and efficient mechanism for reducing cache latency in a coherent cache system.
摘要翻译：用于形成相干高速缓存系统的一部分的数据处理设备包括用于执行数据处理操作的至少一个主设备和耦合到该至少一个主设备的高速缓存，并且被配置为存储由该至少一个主站访问的数据值设备执行数据处理操作。高速缓存一致性电路响应来自相干高速缓存系统的另一部分的一致性请求，以引起关于存储在高速缓存中的至少一个数据值的一致性动作。响应于一致性动作导致高速缓存中至少一个数据值无效的指示，使用重新读取控制电路来发起将该至少一个数据值重新读取到高速缓存中。这种机制导致数据重新取入缓存以由响应于来自相干高速缓存系统的另一部分的一致性请求执行的一致性动作来触发，而不是依赖于由至少一个主设备采取的任何动作，从而提供了一种非常灵活和有效的机制来减少一致的缓存系统中的缓存延迟。

5. 发明申请

US20110087809A1 Reduced latency barrier transaction requests in interconnects 有权
标题翻译：减少互连中的延迟屏障事务请求
公开(公告)号：US20110087809A1
公开(公告)日：2011-04-14
申请号：US12923723
申请日：2010-10-05
申请人： Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
发明人： Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
IPC分类号： G06F13/10
CPC分类号： G06F13/362 , G06F13/1621 , G06F13/1689 , G06F13/364
摘要： Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the interconnect circuitry comprising: at least one input for receiving transaction requests from the at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; at least one path for transmitting the transaction requests between the at least one input and the at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some of said transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some of said transaction requests that occur after said barrier transaction request in said stream of transaction requests; wherein said control circuitry comprises a response signal generator, said response signal generator being responsive to receipt of said barrier transaction request to issue a response signal, said response signal indicating to upstream blocking circuitry that any transaction requests delayed in response to said barrier transaction request can be transmitted further.
摘要翻译：公开了一种用于数据处理设备的互连电路。所述互连电路被配置为提供数据路由，至少一个发起者设备可经由该路径访问至少一个接收方设备，所述互连电路包括：用于从所述至少一个启动器设备接收事务请求的至少一个输入; 用于向所述至少一个接收设备输出交易请求的至少一个输出; 用于在所述至少一个输入和所述至少一个输出之间传送所述事务请求的至少一个路径; 用于将所述接收的交易请求从所述至少一个输入路由到所述至少一个输出的控制电路; 其中所述控制电路被配置为响应于屏障事务请求，以通过不允许重新排序来保持在通过所述至少一个路径之一的事务请求流内关于所述屏障事务请求的至少一些事务请求的排序关于在所述事务流请求中发生在所述屏障事务请求之后发生的所述事务请求中的至少一些的所述事务请求流中的所述屏障事务请求之前发生的所述事务请求中的至少一些; 其中所述控制电路包括响应信号发生器，所述响应信号发生器响应于接收到所述屏障事务请求以发出响应信号，所述响应信号向上游阻塞电路指示响应于所述屏障事务请求而延迟的任何事务请求可以进一步传播。

6. 发明授权

US07599998B2 Message handling communication between a source processor core and destination processor cores 有权
标题翻译：消息处理源处理器核心和目标处理器核心之间的通信
公开(公告)号：US07599998B2
公开(公告)日：2009-10-06
申请号：US10885240
申请日：2004-07-07
申请人： Mark James Galbraith , Harry Samuel Thomas Fearnhamm , Nicholas Esca Smith , Bruce James Mathewson
发明人： Mark James Galbraith , Harry Samuel Thomas Fearnhamm , Nicholas Esca Smith , Bruce James Mathewson
IPC分类号： G06F15/167 , G06F15/76
CPC分类号： G06F15/17
摘要： A data processing apparatus comprises at least one source processor core, at least two destination processor cores, a message handler and a bus arrangement providing a data communication path between the source core, the destination cores and the message handler. The message handler has plurality of message-handling modules. At least one of the message-handling modules has a message receipt indicator that is modifiable by each of the destination processor cores to indicate that a message has been received at its destination. This message-handling module also has a transmission completion detector operable to detect, in dependence upon a message receipt indicator value that a message has been received by all of the at least two destination processor cores and to initiate transmission of an acknowledgement signal to the source processor core.
摘要翻译：数据处理装置包括至少一个源处理器核心，至少两个目的处理器核心，消息处理器和总线装置，其提供源核心，目标核心和消息处理器之间的数据通信路径。消息处理程序具有多个消息处理模块。消息处理模块中的至少一个具有可由每个目的处理器核心修改以指示在其目的地已经接收到消息的消息接收指示符。该消息处理模块还具有传输完成检测器，其可操作用于根据消息接收指示符值来检测消息已被所有至少两个目的处理器核心中的所有接收器接收并且发起确认信号到源处理器核心。

7. 发明授权

US07353297B2 Handling of write transactions in a data processing apparatus 有权
标题翻译：在数据处理设备中处理写事务
公开(公告)号：US07353297B2
公开(公告)日：2008-04-01
申请号：US10862885
申请日：2004-06-08
申请人： Bruce James Mathewson , Antony John Harris
发明人： Bruce James Mathewson , Antony John Harris
IPC分类号： G06F3/00
CPC分类号： G06F13/4059
摘要： A data processing apparatus and method of handling write transactions in such an apparatus is provided. The apparatus has a plurality of devices, and bus circuitry providing connection paths between the plurality of devices. At least one of the devices has a bus master interface operable to generate write transactions for output via the bus circuitry, whilst at least one of the devices has a bus slave interface operable to receive the write transactions from the bus circuitry. A write transaction includes transferring a write address from a bus master interface to a bus slave interface and separately transferring write data from the bus master interface to the bus slave interface. In accordance with embodiments of the present invention, the bus master interface is allowed to generate a write transaction such that the write data is received at the bus slave interface before the associated write address. This leads to a significant decrease in the complexity of the apparatus.
摘要翻译：提供了一种在这种装置中处理写入事务的数据处理装置和方法。该设备具有多个设备，并且总线电路提供多个设备之间的连接路径。至少一个设备具有可操作用于经由总线电路产生用于输出的写入事务的总线主机接口，而至少一个设备具有可操作以从总线电路接收写入事务的总线从接口。写入事务包括将写入地址从总线主机接口传送到总线从站接口，并将写入数据从总线主站接口单独传送到总线从站接口。根据本发明的实施例，允许总线主机接口产生写入事务，使得在相关联的写入地址之前在总线从器件接口处接收写入数据。这导致装置的复杂性的显着降低。

8. 发明授权

US07290075B2 Performing arbitration in a data processing apparatus 有权
标题翻译：在数据处理设备中执行仲裁
公开(公告)号：US07290075B2
公开(公告)日：2007-10-30
申请号：US11431650
申请日：2006-05-11
申请人： Alistair Crone Bruce , Bruce James Mathewson , Antony John Harris
发明人： Alistair Crone Bruce , Bruce James Mathewson , Antony John Harris
IPC分类号： G06F13/14 , G06F13/36 , H04L12/00 , G06F3/00
CPC分类号： G06F13/36
摘要： An apparatus for arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The plurality of paths include a shared connection, the data processing apparatus having a plurality of initiator logic elements for initiating transfers and a plurality of recipient logic elements for receiving transfers, for each transfer the corresponding path coupling the initiator logic element responsible for initiating that transfer with the recipient logic element destined to receive that transfer. The apparatus provides arbitration logic with an indication as to whether the ready signal from a storage element has been asserted, and employs the arbitration logic to select, in dependence on predetermined criteria including at least that indication, one of the plurality of transfers for routing via the shared connection.
摘要翻译：一种用于在数据处理设备之间仲裁的装置，用于在由互连电路提供的相应多个路径上路由多个传输之间。所述多个路径包括共享连接，所述数据处理装置具有用于发起传送的多个启动器逻辑元件和用于接收传送的多个接收者逻辑元件，对于每次传送，耦合起始端逻辑元件的对应路径负责启动该传输收件人逻辑元素注定要接收该传输。该装置向仲裁逻辑提供关于来自存储元件的就绪信号是否已经被断言的指示，并且使用仲裁逻辑根据包括至少该指示的预定标准来选择多个传输中的一个用于路由经过共享连接。

9. 发明授权

US07117277B2 Flexibility of design of a bus interconnect block for a data processing apparatus 有权
标题翻译：用于数据处理设备的总线互连块的设计的灵活性
公开(公告)号：US07117277B2
公开(公告)日：2006-10-03
申请号：US10847576
申请日：2004-05-18
申请人： Bruce James Mathewson , Antony John Harris
发明人： Bruce James Mathewson , Antony John Harris
IPC分类号： G06F3/00
CPC分类号： G06F15/7867
摘要： A method and design tool are provided for modifying a design of a bus interconnect block for a data processing apparatus in order to meet a requirement for a chosen characteristic of the bus interconnect block. The bus interconnect block provides a plurality of connections via which one or more master devices may access one or more slave devices, each connection comprising one or more paths, and each path having one or more path portions separated by storage elements. The method comprises the steps of: (a) selecting one or more candidate paths from said paths; (b) for each candidate path, applying predetermined criteria to determine whether modification of the number of storage elements in said path will assist in meeting the requirement for said chosen characteristic; and (c) modifying the number of storage elements in each candidate path for which it is determined at said step (b) that modification will assist in meeting the requirement for said chosen characteristic. Such an approach allows design modifications to be made iteratively with limited impact on previously made decisions, and allows design modifications to be considered and implemented on a connection-by-connection basis.
摘要翻译：提供了一种方法和设计工具，用于修改用于数据处理设备的总线互连块的设计，以便满足对总线互连块的选定特性的要求。总线互连块提供多个连接，通过该连接，一个或多个主设备可以访问一个或多个从设备，每个连接包括一个或多个路径，并且每个路径具有由存储元件隔开的一个或多个路径部分。该方法包括以下步骤：（a）从所述路径中选择一个或多个候选路径; （b）对于每个候选路径，应用预定标准以确定所述路径中的存储元件的数量的修改是否有助于满足对所选择的特性的要求; 和（c）修改在所述步骤（b）确定的每个候选路径中的存储元件的数量，所述修改将有助于满足对所选择的特性的要求。这种方法允许反复进行设计修改，对先前做出的决策有有限的影响，并且允许在逐个连接的基础上考虑和实现设计修改。

10. 发明授权

US08607006B2 Barrier transactions in interconnects 有权
标题翻译：互连中的障碍事务
公开(公告)号：US08607006B2
公开(公告)日：2013-12-10
申请号：US12923727
申请日：2010-10-05
申请人： Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
发明人： Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F13/1621 , G06F13/1689 , G06F13/364
摘要： Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.
摘要翻译：互连电路被配置为提供数据路由，至少一个发起者设备可经由该路由访问至少一个接收者设备。所述电路包括：用于从至少一个发起者设备接收交易请求的至少一个输入; 用于向所述至少一个接收设备输出交易请求的至少一个输出; 以及用于在至少一个输入和至少一个输出之间传送事务请求的至少一个路径。还包括用于将接收到的交易请求从至少一个输入路由到至少一个输出的控制电路，并且响应于屏障事务请求以维持关于业务流内的所述屏障事务请求的至少一些交易请求的排序沿着所述至少一条路径中的一条通过的请求。阻塞事务请求包括要保持其顺序的事务请求的指示符。

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