专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09224606B2 Method of fabricating semiconductor device isolation structure 有权
标题翻译：制造半导体器件隔离结构的方法
公开(公告)号：US09224606B2
公开(公告)日：2015-12-29
申请号：US13336887
申请日：2011-12-23
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
IPC分类号： H01L21/76 , H01L21/265 , H01L29/66 , H01L29/78
CPC分类号： H01L21/76202 , H01L21/26506 , H01L21/26533 , H01L21/26586 , H01L21/266 , H01L21/324 , H01L21/762 , H01L21/823481 , H01L29/0649 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
摘要翻译：包括可折入隔离结构的半导体器件和用于制造这种器件的方法。优选实施例包括形成至少一个隔离结构的半导体材料的衬底，该隔离结构具有折返轮廓并且隔离一个或多个相邻的操作部件。至少一个隔离结构的折返轮廓由衬底材料形成，并且通过离子注入产生，优选地使用以多个不同角度和能级施加的氧离子。在另一个实施方案中，本发明是形成用于进行至少一个氧离子注入的半导体器件的隔离结构的方法。

2. 发明授权

US08883597B2 Method of fabrication of a FinFET element 有权
标题翻译： FinFET元件的制造方法
公开(公告)号：US08883597B2
公开(公告)日：2014-11-11
申请号：US11831098
申请日：2007-07-31
申请人： Cheng-Hung Chang , Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rang Hsu , Ding-Yuan Chen
发明人： Cheng-Hung Chang , Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rang Hsu , Ding-Yuan Chen
IPC分类号： H01L21/8236 , H01L21/8238 , H01L29/78 , H01L29/66
CPC分类号： H01L21/823828 , H01L21/823807 , H01L21/823821 , H01L21/823857 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.
摘要翻译：本公开提供了一种制造FinFET元件的方法，包括提供包括第一鳍片和第二鳍片的衬底。在第一散热片上形成第一层。第一层包括第一类型的掺杂剂。第二类型的掺杂剂被提供到第二鳍。在包括所形成的第一层和第二类型的掺杂剂的衬底上进行衬底的高温处理。

3. 发明授权

US08173503B2 Fabrication of source/drain extensions with ultra-shallow junctions 有权
标题翻译：源极/漏极扩展与超浅结的制造
公开(公告)号：US08173503B2
公开(公告)日：2012-05-08
申请号：US12617955
申请日：2009-11-13
申请人： Yihang Chiu , Chu-Yun Fu
发明人： Yihang Chiu , Chu-Yun Fu
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814
摘要： A method of forming an integrated circuit device includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a pre-amorphized implantation (PAI) by implanting a first element selected from a group consisting essentially of indium and antimony to a top portion of the semiconductor substrate adjacent to the gate structure. The method further includes, after the step of performing the PAI, implanting a second element different from the first element into the top portion of the semiconductor substrate. The second element includes a p-type element when the first element includes indium, and includes an n-type element when the first element includes antimony.
摘要翻译：形成集成电路器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极结构; 以及通过将选自由铟和锑组成的组中的第一元素注入到与栅极结构相邻的半导体衬底的顶部部分来执行预非晶化注入（PAI）。该方法还包括在执行PAI的步骤之后，将不同于第一元件的第二元件注入到半导体衬底的顶部。当第一元素包括铟时，第二元素包括p型元素，并且当第一元素包括锑时包括n型元素。

4. 发明授权

US07612405B2 Fabrication of FinFETs with multiple fin heights 有权
标题翻译：具有多个翅片高度的FinFET的制造
公开(公告)号：US07612405B2
公开(公告)日：2009-11-03
申请号：US11714644
申请日：2007-03-06
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rung Hsu
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rung Hsu
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses.
摘要翻译：半导体结构包括从半导体衬底的顶表面延伸到半导体衬底中的第一半导体条，其中第一半导体条具有第一高度。第一绝缘区域形成在半导体衬底中并围绕第一半导体条的底部，其中第一绝缘区具有比第一半导体条的顶表面低的第一顶表面。第二半导体条从半导体衬底的顶表面延伸到半导体衬底中，其中第二半导体条的第二高度大于第一高度。第二绝缘区域形成在半导体衬底中并围绕第二半导体条的底部，其中第二绝缘区域具有比第一顶表面低的第二顶表面，并且其中第一绝缘区域和第二绝缘区域基本相同厚度

5. 发明申请

US20090267176A1 A METHOD FOR FORMING A MULTI-LAYER SHALLOW TRENCH ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE 有权
标题翻译：一种在半导体器件中形成多层薄壁分离结构的方法
公开(公告)号：US20090267176A1
公开(公告)日：2009-10-29
申请号：US12111355
申请日：2008-04-29
申请人： Shu-Tine Yang , Chen-Hua Yu , Chu-Yun Fu
发明人： Shu-Tine Yang , Chen-Hua Yu , Chu-Yun Fu
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/76224
摘要： The disclosure describes a multi-layer shallow trench isolation structure in a semiconductor device. The shallow trench isolation structure may include a first void-free, doped oxide layer in the shallow trench, and a second void-free layer above the first doped oxide layer. The first layer may be formed by vapor deposition of precursors of a source of silicon, a source of oxygen and sources of doping materials and making the layer void-free by reflowing the initial layer by an annealing process. The second layer may be formed by vapor deposition of precursors of silicon and doping materials and making the layer void-free by reflowing the initial layer by an annealing process. Alternatively, the second layer may be a silicon oxide layer that may be formed by an atomic layer deposition method. The processing conditions for forming the two layers are different.
摘要翻译：本公开描述了半导体器件中的多层浅沟槽隔离结构。浅沟槽隔离结构可以包括浅沟槽中的第一无空隙掺杂氧化物层，以及在第一掺杂氧化物层上方的第二无空隙层。第一层可以通过气相沉积硅源，氧源和掺杂材料的前体而形成，并通过退火工艺回流初始层使层无空隙。可以通过汽相沉积硅和掺杂材料的前体形成第二层，并通过退火工艺回流初始层使层无空隙。或者，第二层可以是可以通过原子层沉积法形成的氧化硅层。用于形成两层的加工条件不同。

6. 发明申请

US20090233410A1 Self-Aligned Halo/Pocket Implantation for Reducing Leakage and Source/Drain Resistance in MOS Devices 有权
标题翻译：用于降低MOS器件泄漏和源极/漏极电阻的自对准光晕/口袋植入
公开(公告)号：US20090233410A1
公开(公告)日：2009-09-17
申请号：US12048119
申请日：2008-03-13
申请人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
发明人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26586 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.
摘要翻译：一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质，其中所述半导体衬底和所述栅极电介质的侧壁具有接合点; 在所述栅极电介质上形成栅电极; 在所述半导体衬底和所述栅极电极上形成掩模层，其中所述掩模层的与所述接合点相邻的第一部分至少比所述掩模层的离开所述接合点的第二部分更薄; 在形成掩模层的步骤之后，进行晕/穴注入以将卤素/杂质杂质引入到半导体衬底中; 并且在光晕/口袋植入之后去除掩模层。

7. 发明授权

US07371629B2 N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications 有权
标题翻译： N / PMOS饱和电流，HCE和Vt稳定性通过接触蚀刻停止膜修改
公开(公告)号：US07371629B2
公开(公告)日：2008-05-13
申请号：US10314689
申请日：2002-12-09
申请人： Chu-Yun Fu , Chi-Hsun Hsieh , Yi-Ming Sheu , Syun-Ming Jang
发明人： Chu-Yun Fu , Chi-Hsun Hsieh , Yi-Ming Sheu , Syun-Ming Jang
IPC分类号： H01L21/8237
CPC分类号： H01L21/0217 , H01L21/02274 , H01L21/28247 , H01L21/3185 , H01L21/823814 , H01L21/823835
摘要： A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the nitride and then contact holes are fabricated through the dielectric layer and nitride layer to silicide regions and are filled with a metal. For NMOS transistors, silane and NH3 flow rates and a 400° C. temperature are critical in improving NMOS short channel Idsat. Hydrogen content in the nitride is increased by higher NH3 and SiH4 flow rates but does not significantly degrade HCE and Vt. With PMOS transistors, deposition temperature is increased to 550° C. to reduce hydrogen content and improve HCE and Vt stability.
摘要翻译：提供了一种用于改善NMOS和PMOS晶体管中的Idsat的方法。在MOSFET制造方案中，通过PECVD技术在STI和硅化物区域和侧壁间隔物上沉积氮化硅蚀刻停止层。在氮化物上形成介电层，然后通过电介质层和氮化物层到硅化物区域制造接触孔，并填充金属。对于NMOS晶体管，硅烷和NH 3 3流速和400℃的温度对于改善NMOS短沟道Idsat至关重要。氮化物中的氢含量通过较高的NH 3和SiH 4 O 3流速而增加，但不会显着降低HCE和Vt。使用PMOS晶体管，沉积温度增加到550° C.降低氢含量，提高HCE和Vt稳定性。

8. 发明授权

US07297632B2 Scratch reduction for chemical mechanical polishing 有权
标题翻译：化学机械抛光刮刮
公开(公告)号：US07297632B2
公开(公告)日：2007-11-20
申请号：US11082517
申请日：2005-03-17
申请人： Chuang-Ping Hou , Syun-Ming Jang , Ying-Ho Chen , Chu-Yun Fu , Tung-Ching Tseng
发明人： Chuang-Ping Hou , Syun-Ming Jang , Ying-Ho Chen , Chu-Yun Fu , Tung-Ching Tseng
IPC分类号： H01L21/311
CPC分类号： H01L21/31053
摘要： A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish pad, interrupting the first CMP process, cleaning the semiconductor device and the first polish pad, and performing a second CMP process for removing a second portion of the oxide surface.
摘要翻译：提供了一种利用化学机械抛光（CMP）工艺形成半导体器件的方法。在一个示例中，该方法包括依次执行第一CMP处理，以使用高选择性浆料（HSS）和第一抛光垫去除半导体器件的氧化物表面的第一部分，中断第一CMP工艺，清洁半导体器件和第一抛光垫，并且执行用于去除氧化物表面的第二部分的第二CMP工艺。

9. 发明授权

US07118987B2 Method of achieving improved STI gap fill with reduced stress 有权
标题翻译：实现改善STI间隙填充减少应力的方法
公开(公告)号：US07118987B2
公开(公告)日：2006-10-10
申请号：US10767657
申请日：2004-01-29
申请人： Chu-Yun Fu , Chih-Cheng Lu , Syun-Ming Jang
发明人： Chu-Yun Fu , Chih-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L21/76
CPC分类号： H01L21/76235 , A61F2/958 , A61F2002/9583 , A61F2250/0098 , A61M25/001 , A61M25/005 , A61M25/0054 , A61M25/0068 , A61M25/0069 , A61M25/008 , A61M25/0108 , A61M25/0127 , A61M25/1027 , A61M2025/1079 , A61M2025/1093 , A61M2205/32
摘要： A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; dry etching a trench in the semiconductor substrate according to the at least one patterned hardmask layer; forming one or more liner layers to line the trench selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride; forming one or more layers of trench filling material comprising silicon dioxide to backfill the trench; carrying out at least one thermal annealing step to relax accumulated stress in the trench filling material; carrying out at least one of a CMP and dry etch process to remove excess trench filling material above the trench level; and, removing the at least one patterned hardmask layer.
摘要翻译：一种浅沟槽隔离（STI）结构及其形成方法，其具有减小的应力以改善电荷迁移率，该方法包括提供包括覆盖在半导体衬底上的至少一个图案化硬掩模层的半导体衬底; 根据所述至少一个图案化硬掩模层干蚀刻所述半导体衬底中的沟槽; 形成一个或多个衬垫层以使选自二氧化硅，氮化硅和氮氧化硅的沟槽的沟槽; 形成包含二氧化硅的一层或多层沟槽填充材料以回填沟槽; 进行至少一个热退火步骤以缓和沟槽填充材料中的累积应力; 执行CMP和干蚀刻工艺中的至少一个以去除沟槽高度上的多余沟槽填充材料; 以及去除所述至少一个图案化的硬掩模层。

10. 发明申请

US20060049036A1 Method and apparatus for real-time control and monitor of deposition processes 审中-公开
标题翻译：用于实时控制和监测沉积过程的方法和装置
公开(公告)号：US20060049036A1
公开(公告)日：2006-03-09
申请号：US10936905
申请日：2004-09-09
申请人： Cheng-Hung Chang , Jhi-Cherng Lu , Joung-Wei Liou , Chu-Yun Fu , Weng Chang , Syung-Ming Jang
发明人： Cheng-Hung Chang , Jhi-Cherng Lu , Joung-Wei Liou , Chu-Yun Fu , Weng Chang , Syung-Ming Jang
IPC分类号： C23C14/00
CPC分类号： C23C14/34 , C23C14/54
摘要： A method comprises measuring an RF voltage and ion current at a wafer during a plasma-enhanced deposition process, determining a sputter rate in response to the RF voltage and ion current measurements, detecting an abnormal condition in response to one of the RF voltage and ion current measurements, and sputter rate, and taking a corrective action in response to detecting an abnormal condition.
摘要翻译：一种方法包括在等离子体增强沉积过程期间测量晶片处的RF电压和离子电流，响应于RF电压和离子电流测量确定溅射速率，响应于RF电压和离子之一检测异常状况电流测量和溅射速率，并且响应于检测到异常状况采取校正动作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式