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1. 发明申请

US20110128658A1 ESD PROTECTION APPARATUS AND ESD DEVICE THEREIN 有权
标题翻译： ESD保护装置及其ESD器件
公开(公告)号：US20110128658A1
公开(公告)日：2011-06-02
申请号：US12628188
申请日：2009-11-30
申请人： Yu-Ti SU , Chung-Ti HSU
发明人： Yu-Ti SU , Chung-Ti HSU
IPC分类号： H02H9/04 , H01L29/78 , H01L29/73
CPC分类号： H01L27/0285 , H01L29/7436 , H01L29/749
摘要： An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a source region and a drain region. The source region is to be coupled to a low-level voltage. The drain region is disposed apart from the source region and includes a first P-type heavily doped region and at least one first N-type heavily doped region. The first P-type heavily doped region is configured to couple to a pad, and the first N-type heavily doped region is adjacent to the first P-type heavily doped region and floated. An electrostatic discharge protection apparatus is also disclosed herein.
摘要翻译：提供静电放电（ESD）保护装置。 ESD保护器件包括源极区域和漏极区域。源极区域将被耦合到低电平电压。漏极区域与源极区域分开设置并且包括第一P型重掺杂区域和至少一个第一N型重掺杂区域。第一P型重掺杂区域被配置为耦合到焊盘，并且第一N型重掺杂区域与第一P型重掺杂区域相邻并浮动。本文还公开了静电放电保护装置。

2. 发明申请

US20110121394A1 CHIP AND ELECTROSTATIC DISCHARGE PROTECTION DEVICE THEREOF 有权
标题翻译：芯片和静电放电保护装置
公开(公告)号：US20110121394A1
公开(公告)日：2011-05-26
申请号：US12904171
申请日：2010-10-14
申请人： Yu-Ti Su , Chung-Ti Hsu
发明人： Yu-Ti Su , Chung-Ti Hsu
IPC分类号： H01L23/60
CPC分类号： H01L23/60 , H01L24/05 , H01L27/0262 , H01L29/0692 , H01L29/87 , H01L2924/01019 , H01L2924/01077 , H01L2924/12036 , H01L2924/13034 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00
摘要： An ESD protection device is provided, which includes a P-type doped region, an N-type doped region, a first P+ doped region, a first N+ doped region, a second N+ doped region and a third N+ doped region. The N-type doped region is located in the P-type doped region. The first P+ doped region connected to a pad is located in the N-type doped region. A part of the first N+ doped region is located in the N-type doped region and the residue part thereof is located in the P-type doped region. The second and the third N+ doped regions are located in the P-type doped region and outside the N-type doped region, and are respectively electrically connected to a first power rail and a second power rail. In addition, the second N+ doped region is located between the first and the third N+ doped regions.
摘要翻译：提供了ESD保护装置，其包括P型掺杂区域，N型掺杂区域，第一P +掺杂区域，第一N +掺杂区域，第二N +掺杂区域和第三N +掺杂区域。 N型掺杂区域位于P型掺杂区域中。连接到焊盘的第一P +掺杂区域位于N型掺杂区域中。第一N +掺杂区域的一部分位于N型掺杂区域中，其残留部分位于P型掺杂区域中。第二和第三N +掺杂区域位于P型掺杂区域中并且位于N型掺杂区域外部，并且分别电连接到第一电力轨道和第二电力轨道。此外，第二N +掺杂区位于第一和第三N +掺杂区之间。

3. 发明申请

US20070096213A1 Electro-static discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US20070096213A1
公开(公告)日：2007-05-03
申请号：US11454727
申请日：2006-06-16
申请人： Chia-Ku Tsai , Chung-Ti Hsu
发明人： Chia-Ku Tsai , Chung-Ti Hsu
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection circuit comprises a pad, a first transistor, a second transistor, and a diode. Wherein, the first transistor comprises the gate, a first source-drain, and a second source-drain. The first source-drain of the first transistor is electrically coupled to the pad, and the second source-drain of the first transistor is electrically coupled to a first power line. The first source-drain of the second transistor is electrically coupled to the gate of the first transistor, the second source-drain of the second transistor is electrically coupled to the first power line, and the gate of the second transistor is electrically coupled to a second power line. The diode includes a first terminal coupled to the gate of the first transistor, and a second terminal coupled to the pad. In addition, the diode and the first transistor together form a silicon controlled rectifier (SCR).
摘要翻译：静电放电保护电路包括焊盘，第一晶体管，第二晶体管和二极管。其中，第一晶体管包括栅极，第一源极 - 漏极和第二源极 - 漏极。第一晶体管的第一源极 - 漏极电耦合到焊盘，并且第一晶体管的第二源极 - 漏极电耦合到第一电力线。第二晶体管的第一源极 - 漏极电耦合到第一晶体管的栅极，第二晶体管的第二源极 - 漏极电耦合到第一电力线，并且第二晶体管的栅极电耦合到第二条电力线。二极管包括耦合到第一晶体管的栅极的第一端子和耦合到焊盘的第二端子。此外，二极管和第一晶体管一起形成可控硅整流器（SCR）。

4. 发明授权

US08384158B2 Chip and electrostatic discharge protection device thereof 有权
标题翻译：芯片和静电放电保护装置
公开(公告)号：US08384158B2
公开(公告)日：2013-02-26
申请号：US12904171
申请日：2010-10-14
申请人： Yu-Ti Su , Chung-Ti Hsu
发明人： Yu-Ti Su , Chung-Ti Hsu
IPC分类号： H01L23/62
CPC分类号： H01L23/60 , H01L24/05 , H01L27/0262 , H01L29/0692 , H01L29/87 , H01L2924/01019 , H01L2924/01077 , H01L2924/12036 , H01L2924/13034 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00
摘要： An ESD protection device is provided, which includes a P-type doped region, an N-type doped region, a first P+ doped region, a first N+ doped region, a second N+ doped region and a third N+ doped region. The N-type doped region is located in the P-type doped region. The first P+ doped region connected to a pad is located in the N-type doped region. A part of the first N+ doped region is located in the N-type doped region and the residue part thereof is located in the P-type doped region. The second and the third N+ doped regions are located in the P-type doped region and outside the N-type doped region, and are respectively electrically connected to a first power rail and a second power rail. In addition, the second N+ doped region is located between the first and the third N+ doped regions.
摘要翻译：提供了ESD保护装置，其包括P型掺杂区域，N型掺杂区域，第一P +掺杂区域，第一N +掺杂区域，第二N +掺杂区域和第三N +掺杂区域。 N型掺杂区域位于P型掺杂区域中。连接到焊盘的第一P +掺杂区域位于N型掺杂区域中。第一N +掺杂区域的一部分位于N型掺杂区域中，其残留部分位于P型掺杂区域中。第二和第三N +掺杂区域位于P型掺杂区域中并且位于N型掺杂区域外部，并且分别电连接到第一电力轨道和第二电力轨道。此外，第二N +掺杂区位于第一和第三N +掺杂区之间。

5. 发明申请

US20100128401A1 ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND DEVICE 有权
标题翻译：静电放电保护电路和器件
公开(公告)号：US20100128401A1
公开(公告)日：2010-05-27
申请号：US12397352
申请日：2009-03-04
申请人： Ming-Fang Lai , Chung-Ti Hsu
发明人： Ming-Fang Lai , Chung-Ti Hsu
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a first rail, a second rail, a first transistor and a resistance unit. The drain of the first transistor is electrically coupled to the first rail, and the source and gate of the first transistor are electrically coupled to the second rail. The resistance unit is electrically coupled between a body of the first transistor and the second rail. When ESD occurs, the resistance unit provides a resistance between the body of the first transistor and the second rail. An ESD protection device is also provided.
摘要翻译：提供静电放电（ESD）保护电路。 ESD保护电路包括第一导轨，第二导轨，第一晶体管和电阻单元。第一晶体管的漏极电耦合到第一导轨，并且第一晶体管的源极和栅极电耦合到第二导轨。电阻单元电耦合在第一晶体管的主体和第二导轨之间。当ESD发生时，电阻单元在第一晶体管的主体和第二导轨之间提供电阻。还提供ESD保护装置。

6. 发明授权

US07538998B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US07538998B2
公开(公告)日：2009-05-26
申请号：US11454727
申请日：2006-06-16
申请人： Chia-Ku Tsai , Chung-Ti Hsu
发明人： Chia-Ku Tsai , Chung-Ti Hsu
IPC分类号： H02H3/22
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection circuit comprises a pad, a first transistor, a second transistor, and a diode. Wherein, the first transistor comprises the gate, a first source-drain, and a second source-drain. The first source-drain of the first transistor is electrically coupled to the pad, and the second source-drain of the first transistor is electrically coupled to a first power line. The first source-drain of the second transistor is electrically coupled to the gate of the first transistor, the second source-drain of the second transistor is electrically coupled to the first power line, and the gate of the second transistor is electrically coupled to a second power line. The diode includes a first terminal coupled to the gate of the first transistor, and a second terminal coupled to the pad. In addition, the diode and the first transistor together form a silicon controlled rectifier (SCR).
摘要翻译：静电放电保护电路包括焊盘，第一晶体管，第二晶体管和二极管。其中，第一晶体管包括栅极，第一源极 - 漏极和第二源极 - 漏极。第一晶体管的第一源极 - 漏极电耦合到焊盘，并且第一晶体管的第二源极 - 漏极电耦合到第一电力线。第二晶体管的第一源极 - 漏极电耦合到第一晶体管的栅极，第二晶体管的第二源极 - 漏极电耦合到第一电力线，并且第二晶体管的栅极电耦合到第二条电力线。二极管包括耦合到第一晶体管的栅极的第一端子和耦合到焊盘的第二端子。此外，二极管和第一晶体管一起形成可控硅整流器（SCR）。

7. 发明授权

US08405941B2 ESD protection apparatus and ESD device therein 有权
标题翻译： ESD保护装置和ESD装置
公开(公告)号：US08405941B2
公开(公告)日：2013-03-26
申请号：US12628188
申请日：2009-11-30
申请人： Yu-Ti Su , Chung-Ti Hsu
发明人： Yu-Ti Su , Chung-Ti Hsu
IPC分类号： H02H9/00 , H02H3/22
CPC分类号： H01L27/0285 , H01L29/7436 , H01L29/749
摘要： An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a source region and a drain region. The source region is to be coupled to a low-level voltage. The drain region is disposed apart from the source region and includes a first P-type heavily doped region and at least one first N-type heavily doped region. The first P-type heavily doped region is configured to couple to a pad, and the first N-type heavily doped region is adjacent to the first P-type heavily doped region and floated. An electrostatic discharge protection apparatus is also disclosed herein.
摘要翻译：提供一种静电放电（ESD）保护装置。 ESD保护器件包括源极区域和漏极区域。源极区域将被耦合到低电平电压。漏极区域与源极区域分开设置并且包括第一P型重掺杂区域和至少一个第一N型重掺杂区域。第一P型重掺杂区域被配置为耦合到焊盘，并且第一N型重掺杂区域与第一P型重掺杂区域相邻并浮动。本文还公开了静电放电保护装置。

8. 发明授权

US08194370B2 Electrostatic discharge protection circuit and device 有权
标题翻译：静电放电保护电路及器件
公开(公告)号：US08194370B2
公开(公告)日：2012-06-05
申请号：US12397352
申请日：2009-03-04
申请人： Ming-Fang Lai , Chung-Ti Hsu
发明人： Ming-Fang Lai , Chung-Ti Hsu
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a first rail, a second rail, a first transistor and a resistance unit. The drain of the first transistor is electrically coupled to the first rail, and the source and gate of the first transistor are electrically coupled to the second rail. The resistance unit is electrically coupled between a body of the first transistor and the second rail. When ESD occurs, the resistance unit provides a resistance between the body of the first transistor and the second rail. An ESD protection device is also provided.
摘要翻译：提供静电放电（ESD）保护电路。 ESD保护电路包括第一导轨，第二导轨，第一晶体管和电阻单元。第一晶体管的漏极电耦合到第一导轨，并且第一晶体管的源极和栅极电耦合到第二导轨。电阻单元电耦合在第一晶体管的主体和第二导轨之间。当ESD发生时，电阻单元在第一晶体管的主体和第二导轨之间提供电阻。还提供ESD保护装置。

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