专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180108664A1 Memory Devices Using Etching Stop Layers 有权
公开(公告)号：US20180108664A1
公开(公告)日：2018-04-19
申请号：US15604028
申请日：2017-05-24
申请人： Jeong Gil Lee , Jee Yong Kim , Jung Hwan Lee , Dae Seok Byeon , Hyun Seok Lim
发明人： Jeong Gil Lee , Jee Yong Kim , Jung Hwan Lee , Dae Seok Byeon , Hyun Seok Lim
IPC分类号： H01L27/1157 , H01L27/11524 , H01L23/535 , H01L29/06 , H01L29/788 , H01L29/792 , H01L29/423 , G11C16/10 , G11C16/26 , G11C16/08
CPC分类号： H01L27/1157 , G11C16/08 , G11C16/10 , G11C16/26 , H01L23/535 , H01L27/11524 , H01L27/11575 , H01L27/11582 , H01L29/0649 , H01L29/42328 , H01L29/42344 , H01L29/788 , H01L29/792
摘要： A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

2. 发明授权

US09899394B2 Vertical memory devices having contact plugs contacting stacked gate electrodes 有权
公开(公告)号：US09899394B2
公开(公告)日：2018-02-20
申请号：US15001877
申请日：2016-01-20
申请人： Sung-Min Hwang , Jee-Yong Kim , Dae-Seok Byeon
发明人： Sung-Min Hwang , Jee-Yong Kim , Dae-Seok Byeon
IPC分类号： H01L27/115 , H01L27/11578 , H01L27/11575 , H01L27/11573 , H01L27/11565 , H01L27/1157 , H01L27/11563 , H01L27/11582
CPC分类号： H01L27/115 , H01L27/11563 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： A vertical memory device includes a plurality of gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate, a channel extending in the vertical direction on the substrate and penetrating through the gate electrodes, and a plurality of contact plugs extending in the vertical direction and contacting the gate electrodes, respectively. At least one second contact plug is formed on a first gate electrode among the plurality of gate electrodes, and extends in the vertical direction.

3. 发明申请

US20170092657A1 SEMICONDUCTOR DEVICES INCLUDING GATE INSULATION LAYERS ON CHANNEL MATERIALS AND METHODS OF FORMING THE SAME 审中-公开
公开(公告)号：US20170092657A1
公开(公告)日：2017-03-30
申请号：US15375387
申请日：2016-12-12
申请人： Jung-Hwan LEE , Jee-Yong KIM , Dae-Seok BYEON
发明人： Jung-Hwan LEE , Jee-Yong KIM , Dae-Seok BYEON
IPC分类号： H01L27/11582 , H01L29/423 , H01L21/28 , H01L29/66
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11565 , H01L27/1157 , H01L29/42352 , H01L29/66833
摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

4. 发明申请

US20170069390A1 MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF OPERATING MEMORY DEVICE 审中-公开
标题翻译：存储器件，存储器系统和操作存储器件的方法
公开(公告)号：US20170069390A1
公开(公告)日：2017-03-09
申请号：US15357291
申请日：2016-11-21
申请人： SANG-WAN NAM , DOO-HYUN KIM , DAE-SEOK BYEON , CHl-WEON YOON
发明人： SANG-WAN NAM , DOO-HYUN KIM , DAE-SEOK BYEON , CHl-WEON YOON
IPC分类号： G11C16/14 , H01L27/115 , G11C16/34 , G11C16/04 , G11C16/26
CPC分类号： G06F3/0619 , G06F3/061 , G06F3/0644 , G06F3/0655 , G06F3/0688 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/34 , G11C16/3459 , H01L27/11582
摘要： A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.
摘要翻译：如下提供存储器件。存储单元区域包括多个块，每个块包括多个NAND串。控制逻辑基于相对于存储器单元区域的第一边缘的第一距离的较小距离和相对于存储器单元区域的第二边缘的第二距离，将多个块划分为多个块区域，以及使用用于该操作的多个偏置操作参数组来控制在存储单元区域上执行的操作。每个偏差集合与块区域之一相关联。

5. 发明授权

US09355721B2 Resistive memory device and operating method 有权
标题翻译：电阻式存储器件及操作方法
公开(公告)号：US09355721B2
公开(公告)日：2016-05-31
申请号：US14800727
申请日：2015-07-16
申请人： Chi-Weon Yoon , Hyun-Kook Park , Dae-Seok Byeon
发明人： Chi-Weon Yoon , Hyun-Kook Park , Dae-Seok Byeon
IPC分类号： G11C11/34 , G11C16/04 , G11C13/00
CPC分类号： G11C13/0069 , G11C7/04 , G11C11/1675 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C2013/0071 , G11C2013/0083 , G11C2013/0092
摘要： A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.
摘要翻译：操作存储器件的方法包括：通过在连接到所选存储单元的第一信号线上施加第一电压并将第二电压施加到在第一设定写入间隔期间连接到所选存储单元的第二信号线，将预写电压施加到所选择的存储单元，其中所述第一电压的电平高于所述第二电压的电平，然后通过施加具有低于所述第一电压的电平的电平的第三电压并高于所述第一电压的电平而对所选择的存储单元施加写入电压在第二设定写入间隔期间到第一信号线的第二电压。

6. 发明申请

US20160148678A1 CROSS-POINT MEMORY DEVICE INCLUDING MULTI-LEVEL CELLS AND OPERATING METHOD THEREOF 有权
标题翻译：包括多级细胞的交叉点记忆装置及其操作方法
公开(公告)号：US20160148678A1
公开(公告)日：2016-05-26
申请号：US14800060
申请日：2015-07-15
申请人： HYUN-KOOK PARK , CHI-WEON YOON , DAE-SEOK BYEON
发明人： HYUN-KOOK PARK , CHI-WEON YOON , DAE-SEOK BYEON
IPC分类号： G11C13/00 , G11C11/56
CPC分类号： G11C13/004 , G11C11/1659 , G11C11/1673 , G11C11/56 , G11C11/5607 , G11C11/5642 , G11C13/0002 , G11C2013/0054 , G11C2213/71
摘要： A method of operating a cross-point memory device, having an array of multilevel cells, includes performing a first reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a first state and performing a second reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a second state. A difference between a level of a first voltage used in a first sensing operation and a level of a second voltage used in a second sensing operation in the first reading operation is different from a difference between a level of a third voltage used in a first sensing operation and a level of a fourth voltage used in a second sensing operation in the second reading operation.
摘要翻译：一种操作具有多电平单元阵列的交叉点存储器件的方法包括通过多个感测操作执行关于多电平单元的第一读取操作，以确定第一状态并执行关于第二读取操作的第二读取操作所述多电平单元通过多个感测操作来确定第二状态。在第一读取操作中使用的第一电压的电平与在第一读取操作中的第二感测操作中使用的第二电压的电平之间的差异不同于在第一感测中使用的第三电压的电平之间的差操作和在第二读取操作中的第二感测操作中使用的第四电压的电平。

7. 发明申请

US20160027485A1 MEMORY DEVICES, MEMORY SYSTEMS, AND RELATED OPERATING METHODS 有权
标题翻译：存储器件，存储器系统和相关操作方法
公开(公告)号：US20160027485A1
公开(公告)日：2016-01-28
申请号：US14683186
申请日：2015-04-10
申请人： HYUN-KOOK PARK , YEONG-TAEK LEE , DAE-SEOK BYEON , CHI-WEON YOON
发明人： HYUN-KOOK PARK , YEONG-TAEK LEE , DAE-SEOK BYEON , CHI-WEON YOON
IPC分类号： G11C7/22 , G06F11/07 , G11C7/12
CPC分类号： G11C7/22 , G06F11/073 , G06F11/076 , G11C7/062 , G11C7/067 , G11C7/1045 , G11C7/12 , G11C7/14 , G11C11/5642 , G11C13/004 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/42 , G11C29/52 , G11C2013/0054 , G11C2213/72
摘要： A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array includes; dividing the memory cells according to cell regions, and independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region.
摘要翻译：一种操作存储器系统的方法，包括：存储单元阵列中包含共同连接到第一信号线的存储单元; 根据单元区域划分存储单元，并且使用从多个读取参考中选择并且分别对应于每个单元区域的读取参考，独立地对设置在每个单元区域中的存储单元执行读取操作。

8. 发明申请

US20120170370A1 NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM EMPLOYING SAME 有权
标题翻译：非易失性存储器件和非易失性存储器系统
公开(公告)号：US20120170370A1
公开(公告)日：2012-07-05
申请号：US13419732
申请日：2012-03-14
申请人： Seung-Jae LEE , Dae-Seok BYEON , Hyun-Chul HA
发明人： Seung-Jae LEE , Dae-Seok BYEON , Hyun-Chul HA
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C16/0408
摘要： A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode.
摘要翻译：非易失性存储器件包括存储单元阵列，行选择电路和电压发生器。存储单元阵列包括第一虚拟存储单元，第二虚拟存储单元和NAND串，其包括通过第一虚拟存储单元和第二虚拟存储单元串联耦合在串选择晶体管和接地选择晶体管之间的多个存储单元记忆单元在读出操作模式期间，将虚拟读出电压施加到耦合到第一虚拟存储器单元的第一伪字线以及耦合到第二虚拟存储单元的第二虚拟字线。在读出操作模式期间，虚拟读出电压具有比在未选择存储单元上施加的读出电压更低的量值。

9. 发明授权

US07957201B2 Flash memory device operating at multiple speeds 有权
标题翻译：闪存设备以多种速度运行
公开(公告)号：US07957201B2
公开(公告)日：2011-06-07
申请号：US12854987
申请日：2010-08-12
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/30 , G11C16/24
摘要： A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.
摘要翻译：操作闪速存储器件的方法包括具有不同操作速度的第一操作模式和第二操作模式。第一和第二操作模式中的每一个包括位线建立间隔和至少一个附加间隔。闪存被分成连接到相应的第一和第二R / W电路的第一和第二垫。在第二操作模式的位线设置间隔期间，闪速存储器以时分方式控制第一和第二R / W电路的操作，以交错第一和第二垫的相应的峰值电流间隔。

10. 发明授权

US07916540B2 Non-volatile memory devices and systems including bad blocks address re-mapped and methods of operating the same 有权
标题翻译：包括坏块的非易失性存储器件和系统重新映射，并且操作它们的方法
公开(公告)号：US07916540B2
公开(公告)日：2011-03-29
申请号：US12122369
申请日：2008-05-16
申请人： Dae Seok Byeon
发明人： Dae Seok Byeon
IPC分类号： G11C11/34
CPC分类号： G11C29/76
摘要： A method of operating a non-volatile memory device included in a memory card can be provided by re-mapping addresses of bad blocks in a first non-volatile MAT in a memory card and re-mapping addresses of bad blocks in a second non-volatile MAT in the memory card, the second non-volatile MAT including blocks that are address mapped with blocks in the first non-volatile MAT. Also a method of scanning a non-volatile memory device for bad blocks can be provided by sequentially scanning blocks in a non-volatile memory device for data indicating that a respective block is a bad block starting at a starting block address that is above a lowermost block address of the non-volatile memory device, wherein the starting block address is based on a yield for the non-volatile memory device.
摘要翻译：可以通过重新映射存储卡中的第一非易失性MAT中的坏块的地址并在第二非易失性存储卡中重新映射坏块的地址来提供操作包括在存储卡中的非易失性存储器件的方法，存储卡中的易失性MAT，第二非易失性MAT包括在第一非易失性MAT中用块映射的地址的块。也可以通过在非易失性存储器件中顺序地扫描块来提供用于扫描不良块的非易失性存储器件的方法，用于指示相应块是从低于最低位置的起始块地址开始的坏块所述非易失性存储器件的块地址，其中所述起始块地址基于所述非易失性存储器件的产量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式