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1. 发明授权

US08427883B2 Setting circuit and integrated circuit including the same 有权
标题翻译：设置电路和集成电路包括相同
公开(公告)号：US08427883B2
公开(公告)日：2013-04-23
申请号：US12980788
申请日：2010-12-29
申请人： Dae-Suk Kim , Chang-Hyun Lee
发明人： Dae-Suk Kim , Chang-Hyun Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/109 , G11C29/46
摘要： A setting circuit includes a selection unit configured to select one of a predefined code and an external code in response to a test signal, and a setting information generation unit configured to generate setting information in response to the code selected by the selection unit.
摘要翻译：设置电路包括：响应于测试信号选择预定码和外部码之一的选择单元;以及设置信息生成单元，用于响应于由选择单元选择的代码生成设置信息。

2. 发明申请

US20120008423A1 SETTING CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权
标题翻译：设置电路和集成电路，包括它们
公开(公告)号：US20120008423A1
公开(公告)日：2012-01-12
申请号：US12980788
申请日：2010-12-29
申请人： Dae-Suk KIM , Chang-Hyun Lee
发明人： Dae-Suk KIM , Chang-Hyun Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/109 , G11C29/46
摘要： A setting circuit includes a selection unit configured to select one of a predefined code and an external code in response to a test signal, and a setting information generation unit configured to generate setting information in response to the code selected by the selection unit.
摘要翻译：设置电路包括：响应于测试信号选择预定码和外部码之一的选择单元;以及设置信息生成单元，用于响应于由选择单元选择的代码生成设置信息。

3. 发明申请

US20080252831A1 Color Filter Substrate for Liquid Crystal Display and Method of Fabricating the Same 有权
标题翻译：用于液晶显示器的滤色器基板及其制造方法
公开(公告)号：US20080252831A1
公开(公告)日：2008-10-16
申请号：US12099561
申请日：2008-04-08
申请人： Cheol Hwan Lee , Yoon Seok Choi , Dae Suk Kim , Suk Choi
发明人： Cheol Hwan Lee , Yoon Seok Choi , Dae Suk Kim , Suk Choi
IPC分类号： G02F1/1335
CPC分类号： G02F1/133514 , G02F2202/16 , G02F2202/22
摘要： A color filter substrate for a liquid crystal display and a method of fabricating the same are provided. The color filter substrate for a liquid crystal display includes: light shielding parts formed on a substrate at predetermined intervals to prevent light leakage; color filter Layers disposed between the light shielding parts and including color filter patterns of red (R), green (G) and blue (B) for implementing a color image; and a transparent conductive layer formed on a rear surface of the substrate, on which the color filter layers are formed, and formed in a porous structure having a plurality of holes spaced at predetermined intervals. Therefore, it is possible to shield an electrostatic field due to external static electricity and improve image display quality, thereby increasing high brightness characteristics and readability.
摘要翻译：提供一种液晶显示器用滤色器基板及其制造方法。用于液晶显示器的滤色器基板包括：以预定间隔形成在基板上以防止漏光的遮光部; 彩色滤光片设置在遮光部分之间并且包括用于实现彩色图像的红色（R），绿色（G）和蓝色（B）的滤色器图案的层; 以及形成在其上形成滤色器层的基板的后表面上并且以具有以预定间隔间隔开的多个孔的多孔结构形成的透明导电层。因此，可以屏蔽由于外部静电引起的静电场，并且提高图像显示质量，从而增加高亮度特性和可读性。

4. 发明申请

US20080136484A1 Sense amplifier control signal generating circuit of semiconductor memory apparatus 失效
标题翻译：半导体存储装置的感应放大器控制信号发生电路
公开(公告)号：US20080136484A1
公开(公告)日：2008-06-12
申请号：US11826924
申请日：2007-07-19
申请人： Dae-Suk Kim , Jong Chern Lee
发明人： Dae-Suk Kim , Jong Chern Lee
IPC分类号： H03H11/26
CPC分类号： G11C7/08
摘要： A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided. The sense amplifier control signal generating circuit includes a timing control unit that models a transmission path of data from a memory cell to a sense amplifier through a bit line and generates a timing control signal at a sensing timing when the sense amplifier starts a sensing operation. A sense amplifier control signal generating unit receives the timing control signal and generates a sense amplifier control signal.
摘要翻译：提供一种半导体存储装置的读出放大器控制信号发生电路。读出放大器控制信号产生电路包括定时控制单元，其通过位线对来自存储单元的数据的传输路径进行建模，并在读出放大器开始感测操作时在感测定时产生定时控制信号。读出放大器控制信号发生单元接收定时控制信号并产生读出放大器控制信号。

5. 发明授权

US09928205B2 Semiconductor apparatus 有权
公开(公告)号：US09928205B2
公开(公告)日：2018-03-27
申请号：US13162702
申请日：2011-06-17
申请人： Dae Suk Kim , Jong Chern Lee , Sang Jin Byeon
发明人： Dae Suk Kim , Jong Chern Lee , Sang Jin Byeon
IPC分类号： G06F13/42 , G11C16/20 , G11C5/02 , G11C5/04 , G11C5/06 , H01L25/065
CPC分类号： G06F13/4247
摘要： A semiconductor apparatus may include a master chip, first to nth slave chips, first to nth slave chip ID generating units, and a master chip ID generating unit. The first to nth slave chip ID generating units are disposed respectively in the first to nth slave chips and connected in series to each other. Each of the first to nth slave chip ID generating units is configured to add a predetermined code value to an mth operation code to generate an (m+1)th operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.

6. 发明授权

US08797814B2 Multi-test apparatus and method for testing a plurailty of semiconductor chips 有权
标题翻译：用于测试半导体芯片的多重测试装置和方法
公开(公告)号：US08797814B2
公开(公告)日：2014-08-05
申请号：US13333487
申请日：2011-12-21
申请人： Dae-Suk Kim
发明人： Dae-Suk Kim
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/12015 , G11C29/1201 , G11C29/14 , G11C29/26 , G11C2029/2602
摘要： An apparatus and method is capable of reducing instantaneously consumed current by allowing write drivers and input buffers not to be simultaneously driven in a multi-test of semiconductor chips. A multi-test apparatus includes an input unit configured to receive data for testing, wherein the data for testing is inputted from a circuit outside of the multi-test apparatus, a plurality of memory banks each including a plurality of memory cells, a plurality of write drivers, corresponding to the respective memory banks, configured to write the test data in the plurality of memory banks, and a write control unit configured to control the plurality of write drivers so that the test data is written in the memory banks in at least two time periods.
摘要翻译：一种装置和方法能够通过允许写入驱动器和输入缓冲器在半导体芯片的多测试中不被同时驱动来减少瞬时消耗的电流。一种多测试装置，包括：被配置为接收用于测试的数据的输入单元，其中，用于测试的数据从多个测试装置外部的电路输入;多个存储体，每个存储体包括多个存储单元;多个存储单元，写入驱动器，对应于相应的存储器组，被配置为将测试数据写入多个存储体中;以及写入控制单元，被配置为控制多个写入驱动器，使得测试数据至少写入存储体两个时期。

7. 发明授权

US08782476B2 Memory and test method for memory 有权
标题翻译：内存和内存的测试方法
公开(公告)号：US08782476B2
公开(公告)日：2014-07-15
申请号：US13338591
申请日：2011-12-28
申请人： Dae-Suk Kim
发明人： Dae-Suk Kim
IPC分类号： G11C29/00 , G11C29/56 , G11C29/48 , G11C29/44 , G11C29/50
CPC分类号： G11C29/56 , G11C29/26 , G11C29/40 , G11C29/44 , G11C29/48 , G11C29/50 , G11C2029/2602
摘要： A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted.
摘要翻译：输出具有第一和第二单元阵列的存储器的测试方法，通过压缩第一单元阵列的输出数据和第二单元阵列的输出数据而获得的第一压缩数据。当第一压缩数据表示存在故障时，第一和第二单元阵列之一的输出数据被锁定为正常数据，并且通过压缩正常数据而获得的第二压缩数据并输出第一和第二单元中的另一个的数据阵列被输出。

8. 发明申请

US20130234139A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20130234139A1
公开(公告)日：2013-09-12
申请号：US13602263
申请日：2012-09-03
申请人： Dae Suk KIM
发明人： Dae Suk KIM
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G01R31/2853 , H01L22/34 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a plurality of stacked slices each configured to have a plurality of vias formed therein so that signals are transferred between the slices arranged in a vertical direction, wherein each of the plurality of slices is configured to transfer a pulse signal, generated during a test section, to a lowest slice of the plurality of slices through the vias connected thereto.
摘要翻译：半导体集成电路包括多个层叠的片，每个层叠的片被配置为具有形成在其中的多个通孔，使得信号在沿垂直方向布置的片之间传输，其中多个片中的每一个被配置为传送产生的脉冲信号在测试部分期间通过与其连接的通孔的多个切片中的最低切片。

9. 发明申请

US20120272108A1 MEMORY AND TEST METHOD FOR MEMORY 有权
标题翻译：存储器的记忆和测试方法
公开(公告)号：US20120272108A1
公开(公告)日：2012-10-25
申请号：US13338591
申请日：2011-12-28
申请人： Dae-Suk Kim
发明人： Dae-Suk Kim
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/56 , G11C29/26 , G11C29/40 , G11C29/44 , G11C29/48 , G11C29/50 , G11C2029/2602
摘要： A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted.
摘要翻译：输出具有第一和第二单元阵列的存储器的测试方法，通过压缩第一单元阵列的输出数据和第二单元阵列的输出数据而获得的第一压缩数据。当第一压缩数据表示存在故障时，第一和第二单元阵列之一的输出数据被锁定为正常数据，并且通过压缩正常数据而获得的第二压缩数据并输出第一和第二单元中的另一个的数据阵列被输出。

10. 发明申请

US20120154008A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20120154008A1
公开(公告)日：2012-06-21
申请号：US13162702
申请日：2011-06-17
申请人： Dae Suk KIM , Jong Chern Lee , Sang Jin Byeon
发明人： Dae Suk KIM , Jong Chern Lee , Sang Jin Byeon
IPC分类号： H03K3/289
CPC分类号： G06F13/4247
摘要： A semiconductor apparatus may include a master chip, first to nth slave chips, first to nth slave chip ID generating units, and a master chip ID generating unit. The first to nth slave chip ID generating units are disposed respectively in the first to nth slave chips and connected in series to each other. Each of the first to nth slave chip ID generating units is configured to add a predetermined code value to an mth operation code to generate an (m+1)th operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, ‘n’ is an integer that is equal to or greater than 2, and ‘m’ is an integer that is equal to or greater than 1 and equal to or smaller than ‘n’.
摘要翻译：半导体装置可以包括主芯片，第一至第n从属芯片，第一至第n从属芯片ID生成单元和主芯片ID生成单元。第1〜第n从属芯片ID生成部分分别配置在第1至第n从属芯片中并串联连接。第一至第n从属芯片ID生成单元中的每一个被配置为向第m个操作码添加预定代码值，以生成第（m + 1）个操作代码。主芯片ID产生单元设置在主芯片中，以响应于选择信号产生可变的第一操作码。这里，'n'为2以上的整数，'m'为1以上且等于或小于'n'的整数。

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