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1. 发明授权

US08898540B1 Counter update through atomic operation 有权
标题翻译：通过原子操作计数器更新
公开(公告)号：US08898540B1
公开(公告)日：2014-11-25
申请号：US13074817
申请日：2011-03-29
申请人： Dan Ilan , Adi Habusha , Noam Mizrahi
发明人： Dan Ilan , Adi Habusha , Noam Mizrahi
IPC分类号： G11C29/00 , G06F11/20 , G06F11/10 , G06F9/38
CPC分类号： G06F11/2053 , G06F9/3004 , G06F9/382 , G06F9/3853 , G06F11/1048 , G06F11/106
摘要： Some of the embodiments of the present disclosure provide a system-on-chip (SOC) that includes a plurality of processing cores; and a counter update module configured to atomically update a counter that is stored in a storage location, based on a counter update command received from a processing core of the plurality of processing cores; generate an ECC for the updated value of the counter; and write the updated value of the counter and the ECC to the storage location. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了包括多个处理核心的片上系统（SOC）; 以及计数器更新模块，被配置为基于从所述多个处理核心的处理核心接收的计数器更新命令，原子地更新存储在存储位置中的计数器; 为计数器的更新值生成一个ECC; 并将计数器和ECC的更新值写入存储位置。还描述和要求保护其他实施例。

2. 发明申请

US20090046700A1 METHOD AND DEVICE FOR MANAGING MULTI-FRAMES 有权
标题翻译：用于管理多个框架的方法和设备
公开(公告)号：US20090046700A1
公开(公告)日：2009-02-19
申请号：US12094124
申请日：2005-11-17
申请人： Eran Glickman , Oren Gelberg , Dan Ilan
发明人： Eran Glickman , Oren Gelberg , Dan Ilan
IPC分类号： H04J3/06
CPC分类号： H04J3/1605 , H04L29/06
摘要： A device having multi-frame transmission and reception capabilities and a method for transmitting and receiving multi-frames. The device includes a processor, a time slot assigner, connected to a communication line via a physical layer unit. The physical layer unit is adapted to generate a communication line clock signal (LINE_TX_CLK1) and a multi-frame synchronization signal (MFRAME_TX_SYNC1). The device is characterized by including a transmit media access controller (MAC) connected to the physical layer unit whereas the MAC is adapted to receive the MFRAME_TX_SYNC1 and LINE_TX_CLK1 signals and in response to scan, during a single multi-frame transmission period, multiple transmit MAC memory entry groups such as to retrieve transmission instructions and in response to enable access to the communication line. Each transmit MAC memory entry group stores transmission instructions that control a transmission of a frame. During a single multi-frame transmission period the transmit MAC accesses at least twice at least one transmit MAC memory entry group; and whereas the processor is adapted to generate the multiple transmission instructions. The processor receives a processor clock signal (PR_CLK) that differs from LINE_TX_CLK1. The MAC also performs reception operations using receive clock and sync signals.
摘要翻译：具有多帧发送和接收能力的装置以及用于发送和接收多帧的方法。该设备包括经由物理层单元连接到通信线路的处理器，时隙分配器。物理层单元适于生成通信线路时钟信号（LINE_TX_CLK1）和多帧同步信号（MFRAME_TX_SYNC1）。该设备的特征在于包括连接到物理层单元的传输介质访问控制器（MAC），而MAC适于接收MFRAME_TX_SYNC1和LINE_TX_CLK1信号，并且响应于扫描，在单个多帧传输周期期间，多个传输MAC 存储器条目组，例如用于检索传输指令并且响应于允许访问通信线路。每个发送MAC存储器条目组存储控制帧的传输的传输指令。在单个多帧传输周期期间，发射MAC至少访问两个至少一个传输MAC存储器入口组; 而处理器适于生成多个传输指令。处理器接收到与LINE_TX_CLK1不同的处理器时钟信号（PR_CLK）。 MAC还使用接收时钟和同步信号来执行接收操作。

3. 发明授权

US08643781B1 Display interface methods and systems 失效
公开(公告)号：US08643781B1
公开(公告)日：2014-02-04
申请号：US12980712
申请日：2010-12-29
申请人： Dan Ilan , Guy Nakibly , Eilon Argov
发明人： Dan Ilan , Guy Nakibly , Eilon Argov
IPC分类号： H04N5/06 , H04N3/14 , H04N9/475
CPC分类号： H04N5/06 , G06F3/1431 , G09G3/2096 , G09G5/006 , G09G5/36 , G09G2310/08 , G09G2370/12 , H04N5/66
摘要： Methods and systems for implementing video driving circuitry are disclosed. For example, in an embodiment, a system for driving a plurality of different types of video devices is disclosed. The system includes, for example, a System on a Chip (SoC) that itself includes a Liquid Crystal Display (LCD) controller circuit configured to generate digital video data, a first synchronization signal for controlling a first characteristic of the digital video data, and a second synchronization signal for controlling a second characteristic of the digital video data. The SoC further includes a delay circuit configured to variably delay the first synchronization signal and the second synchronization signal relative to the digital video data to generate a delayed first synchronization signal and a delayed second synchronization signal.

4. 发明授权

US07707335B2 Device and method for managing a retransmit operation 有权
标题翻译：用于管理重传操作的设备和方法
公开(公告)号：US07707335B2
公开(公告)日：2010-04-27
申请号：US12090116
申请日：2006-02-02
申请人： Gil Lidji , Dan Ilan
发明人： Gil Lidji , Dan Ilan
IPC分类号： G06F3/00 , G06F13/36
CPC分类号： G06F5/12
摘要： A method and device for managing retransmit operations. The device, includes a FIFO memory unit, a read pointer, a retry pointer and a write pointer. The device is characterized by including a gray code state machine connected to an emulated read pointer logic; whereas the gray code state machine is adapted to provide a gray code word representative of a state of a read logic that comprises the read pointer; whereas the emulated read pointer logic is adapted to process at least one gray code word and to provide an emulated read pointer that tracks a FIFO memory unit entry that stores data that was not accepted; whereas the emulated read pointer logic is connected to a write control logic adapted to control writing operations to the FIFO memory unit in response to the emulated read pointer logic; and whereas the read logic receives a read clock that differs from a write clock provided to the emulated read pointer logic and to the write control logic.
摘要翻译：一种用于管理重传操作的方法和设备。该设备包括FIFO存储单元，读指针，重试指针和写指针。该装置的特征在于包括连接到仿真读指针逻辑的灰码状态机; 而灰度状态机适于提供代表包括读指针的读逻辑状态的灰码字; 而仿真读指针逻辑适于处理至少一个灰码字，并提供跟踪存储未被接受的数据的FIFO存储器单元入口的仿真读指针; 而仿真的读指针逻辑连接到写控制逻辑，该写控制逻辑适于响应于仿真的读指针逻辑而控制对FIFO存储器单元的写操作; 而读逻辑接收与提供给仿真读指针逻辑和写控制逻辑的写时钟不同的读时钟。

5. 发明授权

US08543854B1 Method and system for power configuration 有权
标题翻译：功率配置方法和系统
公开(公告)号：US08543854B1
公开(公告)日：2013-09-24
申请号：US12965388
申请日：2010-12-10
申请人： Dan Ilan , Rabeeh Khoury , Tawfik Bayouk
发明人： Dan Ilan , Rabeeh Khoury , Tawfik Bayouk
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3228
摘要： Aspects of the disclosure provide a method for power mode switching. The method includes sending a pausing request to an application executed in an electronic system. The pausing request informs the application of an intent to switch the electronic system from an active mode to a power saving mode that causes the electronic system to pause executing the application. Then, the method includes determining that the application accepts the pausing request, and configuring the electronic system into the power saving mode, such that the application pauses at a pausing point determined in response to the pausing request.
摘要翻译：本公开的方面提供了一种用于功率模式切换的方法。该方法包括向在电子系统中执行的应用发送暂停请求。暂停请求通知应用程序将电子系统从主动模式切换到使电子系统暂停执行应用程序的省电模式的意图。然后，该方法包括确定应用程序接受暂停请求，并将电子系统配置为省电模式，使得应用程序在响应于暂停请求确定的暂停点处暂停。

6. 发明授权

US08963936B1 Method and apparatus for refreshing a display 有权
标题翻译：用于刷新显示器的方法和装置
公开(公告)号：US08963936B1
公开(公告)日：2015-02-24
申请号：US12977815
申请日：2010-12-23
申请人： Rabeeh Khoury , Dan Ilan , Guy Nakibly
发明人： Rabeeh Khoury , Dan Ilan , Guy Nakibly
IPC分类号： G09G5/36 , G09G5/00
CPC分类号： G09G5/395 , G09G5/36 , G09G2330/021 , G09G2340/0435 , G09G2380/14
摘要： Aspects of the disclosure provide an apparatus. The apparatus includes a display module configured to display an image frame on a screen based on pixel data of the image frame, a memory chip configured to include a frame buffer that stores pixel data of image frames to be displayed by the display module and an integrated circuit, such as a system on chip (SOC). The integrated circuit includes a memory controller coupled to the memory chip and configured to access the memory chip to fetch the pixel data from the frame buffer in response to data requests, and a display controller coupled to the display module. The display controller is configured to send data requests to the memory controller to fetch the pixel data from the frame buffer and transmit the pixel data to the display module when the apparatus is in a first mode, such as an active mode. Further, the display controller is configured to selectively drop a portion of the data requests to increase an idle time of the memory chip when the apparatus enters a second mode, such as an e-book mode, so that the memory chip enters a memory power saving mode when the apparatus is in the second mode.
摘要翻译：本公开的方面提供了一种装置。该装置包括：显示模块，被配置为基于图像帧的像素数据在屏幕上显示图像帧;存储器芯片，被配置为包括存储要由显示模块显示的图像帧的像素数据的帧缓冲器;以及集成电路，如片上系统（SOC）。集成电路包括耦合到存储器芯片并被配置为访问存储器芯片以响应于数据请求从帧缓冲器获取像素数据的存储器控制器，以及耦合到显示模块的显示控制器。所述显示控制器被配置为当所述设备处于诸如活动模式的第一模式时，向所述存储器控制器发送数据请求以从所述帧缓冲器获取所述像素数据并将所述像素数据发送到所述显示模块。此外，显示控制器被配置为当设备进入诸如电子书模式的第二模式时选择性地丢弃数据请求的一部分以增加存储器芯片的空闲时间，使得存储器芯片进入存储器电源当设备处于第二模式时的保存模式。

7. 发明授权

US08810589B1 Method and apparatus for refreshing display 有权
标题翻译：用于刷新显示的方法和装置
公开(公告)号：US08810589B1
公开(公告)日：2014-08-19
申请号：US12942178
申请日：2010-11-09
申请人： Rabeeh Khoury , Dan Ilan , Eran Maor
发明人： Rabeeh Khoury , Dan Ilan , Eran Maor
IPC分类号： G06F13/00 , G09G5/39
CPC分类号： G09G5/395 , G09G5/39 , G09G2330/021 , G09G2360/121 , G09G2360/125 , G09G2360/128 , G09G2380/14
摘要： Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a first memory, a memory controller, and a display controller coupled to a display module. The memory controller is selectively coupled to the first memory and to a second memory that has higher power consumption than the first memory. The second memory includes a frame buffer storing pixel data of images to be displayed on the display module. When the integrated circuit enters a power saving mode, the memory controller, while coupled to the first memory and the second memory, pre-fetches pixel data of an image from the second memory into the first memory at a first data rate. Further, when the integrated circuit is in the power saving mode, the display controller streams the pixel data from the first memory to the display module at a second data rate that is lower than the first data rate, and the second memory is configured into a memory power-saving mode after the pre-fetching until the second memory is accessed for additional pixel data.
摘要翻译：本公开的方面提供集成电路。集成电路包括第一存储器，存储器控制器和耦合到显示模块的显示控制器。存储器控制器选择性地耦合到第一存储器和具有比第一存储器更高的功耗的第二存储器。第二存储器包括存储要在显示模块上显示的图像的像素数据的帧缓冲器。当集成电路进入省电模式时，存储器控制器在耦合到第一存储器和第二存储器的同时，以第一数据速率从第二存储器预取图像的像素数据到第一存储器。此外，当集成电路处于省电模式时，显示控制器以比第一数据速率低的第二数据速率将像素数据从第一存储器流向显示模块，并且将第二存储器配置为预取后的存储器省电模式，直到第二个存储器被访问为其他像素数据。

8. 发明授权

US08306011B2 Method and device for managing multi-frames 有权
标题翻译：用于管理多帧的方法和设备
公开(公告)号：US08306011B2
公开(公告)日：2012-11-06
申请号：US12094124
申请日：2005-11-17
申请人： Eran Glickman , Oren Gelberg , Dan Ilan
发明人： Eran Glickman , Oren Gelberg , Dan Ilan
IPC分类号： H04J3/06
CPC分类号： H04J3/1605 , H04L29/06
摘要： A device includes a processor and a time slot assigner, connected to a communication line via a physical layer unit. The physical layer unit is adapted to generate a communication line clock signal and a multi-frame synchronization signal. The device also includes a transmit media access controller (MAC) adapted to receive the multi-frame synchronization signal and the communication line clock signal and in response to scan, during a single multi-frame transmission period, multiple transmit MAC memory entry groups such as to retrieve transmission instructions and in response to enable access to the communication line. During a single multi-frame transmission period the transmit MAC accesses at least twice at least one transmit MAC memory entry group. The processor receives a processor clock signal that differs from the communication line clock signal. The MAC also performs reception operations using receive clock and sync signals.
摘要翻译：一种设备包括经由物理层单元连接到通信线路的处理器和时隙分配器。物理层单元适于产生通信线路时钟信号和多帧同步信号。该设备还包括适于接收多帧同步信号和通信线路时钟信号的传输媒体接入控制器（MAC），并且响应于在单个多帧传输周期期间的扫描响应多个传输MAC存储器条目组，例如以检索传输指令并且响应于允许访问通信线路。在单个多帧传输周期期间，发射MAC至少访问两个至少一个传输MAC存储器条目组。处理器接收与通信线路时钟信号不同的处理器时钟信号。 MAC还使用接收时钟和同步信号来执行接收操作。

9. 发明申请

US20080215306A1 Device and Method for Managing a Retransmit Operation 有权
标题翻译：用于管理重发操作的设备和方法
公开(公告)号：US20080215306A1
公开(公告)日：2008-09-04
申请号：US12090116
申请日：2006-02-02
申请人： Gil Lidji , Dan Ilan
发明人： Gil Lidji , Dan Ilan
IPC分类号： G06F9/455
CPC分类号： G06F5/12
摘要： A method and device for managing retransmit operations. The device, includes a FIFO memory unit, a read pointer, a retry pointer and a write pointer. The device is characterized by including a gray code stat e machine connected to an emulated read pointer logic; whereas the gray code state machine is adapted to provide a gray code word representative of a state of a read logic that comprises the read pointer; whereas the emulated read pointer logic is adapted to process at least one gray code word and to provide an emulated read pointer that tracks a FIFO memory unit entry that stores data that was not accepted; whereas the emulated read pointer logic is connected to a write control logic adapted to control writing operations to the FIFO memory unit in response to the emulated read pointer logic; and whereas the read logic receives a read clock that differs from a write clock provided to the emulated read pointer logic and to the write control logic.
摘要翻译：一种用于管理重传操作的方法和设备。该设备包括FIFO存储单元，读指针，重试指针和写指针。该装置的特征在于包括连接到仿真读指针逻辑的灰度代码机器; 而灰度状态机适于提供代表包括读指针的读逻辑状态的灰码字; 而仿真读指针逻辑适于处理至少一个灰码字，并提供跟踪存储未被接受的数据的FIFO存储器单元入口的仿真读指针; 而仿真的读指针逻辑连接到写控制逻辑，该写控制逻辑适于响应于仿真的读指针逻辑而控制对FIFO存储器单元的写操作; 而读逻辑接收与提供给仿真读指针逻辑和写控制逻辑的写时钟不同的读时钟。

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