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1. 发明申请

US20090217229A1 Wire Structures Minimizing Hostile Neighbors and Coupling Affects 有权
标题翻译：电线结构最小化敌对邻居和耦合影响
公开(公告)号：US20090217229A1
公开(公告)日：2009-08-27
申请号：US12035506
申请日：2008-02-22
申请人： Daniel Lipetz , Joshua M. Weinberg
发明人： Daniel Lipetz , Joshua M. Weinberg
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5077 , G06F2217/82
摘要： A method for minimizing coupling capacitance between wires in a bus that is shifting by way of rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, the coupling capacitance across said bus is uniform and minimized relative to the original arrangement. Alternatively, a method for minimizing coupling capacitance between wires in a bus that is shifting by way of rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, one of said wires incurs the smallest possible amount of coupling capacitance and then the coupling capacitance across the rest of said wires in said bus gets progressively worse relative to the original arrangement.
摘要翻译：一种用于最小化总线中导线之间的耦合电容的方法，该总线通过重新排列所述总线中的所述导线的顺序而移位，使得除了所述布置中的所述第一和最后导线之外，跨所述总线的耦合电容是均匀的并且最小化相对于原来的安排。或者，一种用于使总线中的导线之间的耦合电容最小化的方法，该方法是通过重新排列所述总线中的所述导线的顺序而移位，使得除了所述布置中的所述第一和最后的导线之外，所述布线中的一个导致最小的可能耦合电容量，然后在所述总线中的所述电线的其余部分的耦合电容相对于原始布置逐渐变差。

2. 发明申请

US20070294330A1 SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING A COMBINED MODULI-9 AND 3 RESIDUE GENERATOR 失效
标题翻译：用于提供组合MODULI-9和3残留发电机的系统，方法和计算机程序产品
公开(公告)号：US20070294330A1
公开(公告)日：2007-12-20
申请号：US11425185
申请日：2006-06-20
申请人： Daniel Lipetz , Bruce M. Fleischer , Eric M. Schwarz
发明人： Daniel Lipetz , Bruce M. Fleischer , Eric M. Schwarz
IPC分类号： G06F7/38
CPC分类号： G06F7/72 , G06F7/727
摘要： Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator. The methods include receiving a number in binary coded decimal (BCD) or binary format. A modulus-9 residue of the number is calculated. The modulus-9 residue that is calculated includes a modulus-3 residue of the number. The modulis-3 residue of the number is output. If the number is in BCD format, then the modulus-9 residue of the number is output.
摘要翻译：用于提供组合模块9和3残留发生器的系统，方法和计算机程序产品。这些方法包括接收二进制编码十进制（BCD）或二进制格式的数字。计算该数的9个模数。计算出的模数为9的残差包括该数目的3的残基。输出的模数3个残差。如果数字为BCD格式，则输出该数字的9个模数。

3. 发明授权

US07721171B2 Scheme to optimize scan chain ordering in designs 有权
标题翻译：优化设计中扫描链排序的方案
公开(公告)号：US07721171B2
公开(公告)日：2010-05-18
申请号：US11839648
申请日：2007-08-16
申请人： Mark A. Erle , Bruce M. Fleischer , Daniel Lipetz
发明人： Mark A. Erle , Bruce M. Fleischer , Daniel Lipetz
IPC分类号： G01R31/28
CPC分类号： G01R31/318591 , G06F17/505 , G06F2217/14
摘要： A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided. The method comprising: creating a schematic representative of a circuit design having a first cell and a second cell, the first cell and the second cell each having latches therein; creating a scan input pin and a scan output pin for each of the latches in the first cell and the second cell on the schematic; generating a first label on the schematic to provide a first wiring arrangement for the latches in the circuit design, the first wiring arrangement identifies a first order to which the scan input of each of the latches is wired to the scan output of another one of the latches; creating a layout representative of the circuit design; generating a first scan chain having a first length on the layout based on the first wiring arrangement; creating a second scan chain from the first scan chain on the layout, the second scan chain having a second length less than the first length of the first scan chain; and generating a second label on the schematic based on the second scan chain, the second label provides a second wiring arrangement for the latches in the circuit design, the second wiring arrangement identifies a second order to which the scan input of each of the latches is wired to the scan output of another one of the latches.
摘要翻译：提供了一种在电子计算机辅助设计系统中优化电路设计中的扫描链排序的方法。该方法包括：创建具有第一单元和第二单元的电路设计的示意图，第一单元和第二单元各自在其中具有锁存器; 为第一个单元中的每个锁存器和原理图上的第二个单元创建扫描输入引脚和扫描输出引脚; 在原理图上产生第一标签以提供用于电路设计中的锁存器的第一布线布置，第一布线布置识别每个锁存器的扫描输入被连接到另一个的另一个的扫描输出的第一顺序锁存器创建一个代表电路设计的布局; 基于第一布线布置在布局上产生具有第一长度的第一扫描链; 在所述布局上从所述第一扫描链创建第二扫描链，所述第二扫描链具有小于所述第一扫描链的所述第一长度的第二长度; 并且基于所述第二扫描链在所述原理图上产生第二标签，所述第二标签为所述电路设计中的所述锁存器提供第二布线布置，所述第二布线布置识别每个所述闩锁的扫描输入的第二顺序连接到另一个锁存器的扫描输出。

4. 发明授权

US07962880B2 Wire structures minimizing coupling effects between wires in a bus 有权
标题翻译：电线结构使母线电线之间的耦合效应最小化
公开(公告)号：US07962880B2
公开(公告)日：2011-06-14
申请号：US12035506
申请日：2008-02-22
申请人： Daniel Lipetz , Joshua M. Weinberg
发明人： Daniel Lipetz , Joshua M. Weinberg
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5077 , G06F2217/82
摘要： A method for minimizing coupling capacitance between wires in a bus comprising shifting by rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, the coupling capacitance across said bus is uniform and minimized relative to the original arrangement. Alternatively, a method for minimizing coupling capacitance between wires in a bus comprising shifting by rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, one of said wires incurs the smallest possible amount of coupling capacitance and then the coupling capacitance across the rest of said wires in said bus gets progressively worse relative to the original arrangement.
摘要翻译：一种用于最小化总线中的线之间的耦合电容的方法，包括通过重新排列所述总线中的所述导线的顺序来移位，使得除了所述布置中的所述第一和最后导线之外，跨所述总线的耦合电容是均匀的并且相对于原来的安排。或者，一种用于使总线中的线之间的耦合电容最小化的方法，包括通过重新排列所述总线中的所述线的顺序来移位，使得除了所述布置中的所述第一和最后的导线之外，所述线中的一个导致最小可能量的耦合然后在所述总线中的所述电线的其余部分的耦合电容相对于原始布置逐渐变差。

5. 发明授权

US07865950B2 System of assigning permissions to a user by password 有权
标题翻译：通过密码向用户分配权限的系统
公开(公告)号：US07865950B2
公开(公告)日：2011-01-04
申请号：US11764842
申请日：2007-06-19
申请人： Daniel Lipetz
发明人： Daniel Lipetz
IPC分类号： G06F7/04 , G06F17/30 , H04L9/00
CPC分类号： G06F21/6218 , G06F2221/2141
摘要： A data processing system includes a data storage unit for storing data sets accessible to a user upon receipt of permission. The data processing system restricts access to data sets by requiring a username and then requiring a password to obtain permission for access to a data set stored in a data storage unit. The system is adapted to support use of more than one said password associated with a username; and each of those passwords associated with that username permits a distinct level of access to a particular data set, whereas other passwords can provide different levels of access to any data set assigned thereto.
摘要翻译：数据处理系统包括数据存储单元，用于在接收到许可时存储用户可访问的数据集。数据处理系统通过要求用户名然后需要密码来获得访问存储在数据存储单元中的数据集的权限来限制对数据集的访问。该系统适于支持使用与用户名相关联的多个所述密码; 并且与该用户名相关联的每个密码允许对特定数据集的不同级别的访问，而其他密码可以为分配给其的任何数据集提供不同级别的访问。

6. 发明授权

US08566385B2 Decimal floating point multiplier and design structure 失效
标题翻译：十进制浮点乘数和设计结构
公开(公告)号：US08566385B2
公开(公告)日：2013-10-22
申请号：US12629081
申请日：2009-12-02
申请人： Steven R Carlough , Daniel Lipetz , Joshua M Weinberg
发明人： Steven R Carlough , Daniel Lipetz , Joshua M Weinberg
IPC分类号： G06F7/52
CPC分类号： G06F7/4915 , G06F2207/4911
摘要： Several implementations and a design structure for decimal multiplication that uses a BCD 4221 encoding scheme, separate accumulation of partial products, accumulation of the partial products into a final product and conversion from and to a BCD 8421 coding scheme.
摘要翻译：使用BCD 4221编码方案的小数乘法的几种实现和设计结构，部分乘积的单独积累，部分乘积的累积到最终产品以及从BCD 8421编码方案的转换。

7. 发明申请

US20110131266A1 Decimal Floating Point Multiplier and Design Structure 失效
标题翻译：十进制浮点乘数和设计结构
公开(公告)号：US20110131266A1
公开(公告)日：2011-06-02
申请号：US12629081
申请日：2009-12-02
申请人： Steven R. Carlough , Daniel Lipetz , Joshua M. Weinberg
发明人： Steven R. Carlough , Daniel Lipetz , Joshua M. Weinberg
IPC分类号： G06F7/52
CPC分类号： G06F7/4915 , G06F2207/4911
摘要： Several implementations and a design structure for decimal multiplication that uses a BCD 4221 encoding scheme, separate accumulation of partial products, accumulation of the partial products into a final product and conversion from and to a BCD 8421 coding scheme.
摘要翻译：使用BCD 4221编码方案的小数乘法的几种实现和设计结构，部分乘积的单独积累，部分乘积的累积到最终产品以及从BCD 8421编码方案的转换。

8. 发明授权

US07739323B2 Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator 失效
标题翻译：用于提供组合模9和3残留发生器的系统，方法和计算机程序产品
公开(公告)号：US07739323B2
公开(公告)日：2010-06-15
申请号：US11425185
申请日：2006-06-20
申请人： Daniel Lipetz , Bruce M. Fleischer , Eric M. Schwarz
发明人： Daniel Lipetz , Bruce M. Fleischer , Eric M. Schwarz
IPC分类号： G06F7/38
CPC分类号： G06F7/72 , G06F7/727
摘要： Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator. The methods include receiving a number in binary coded decimal (BCD) or binary format. A modulus-9 residue of the number is calculated. The modulus-9 residue that is calculated includes a modulus-3 residue of the number. The modulus-3 residue of the number is output. If the number is in BCD format, then the modulus-9 residue of the number is output.
摘要翻译：用于提供组合模9和3残留发生器的系统，方法和计算机程序产品。这些方法包括接收二进制编码十进制（BCD）或二进制格式的数字。计算该数的模数-9残基。计算的模数-9残基包括该数目的模数-3残基。输出该数的模数-3残差。如果数字为BCD格式，则输出数字的模数-9个残差。

9. 发明申请

US20090049353A1 SCHEME TO OPTIMIZE SCAN CHAIN ORDERING IN DESIGNS 有权
标题翻译：计划优化设计中的链条订单
公开(公告)号：US20090049353A1
公开(公告)日：2009-02-19
申请号：US11839648
申请日：2007-08-16
申请人： Mark A. Erle , Bruce M. Fleischer , Daniel Lipetz
发明人： Mark A. Erle , Bruce M. Fleischer , Daniel Lipetz
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318591 , G06F17/505 , G06F2217/14
摘要： A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided. The method comprising: creating a schematic representative of a circuit design having a first cell and a second cell, the first cell and the second cell each having latches therein; creating a scan input pin and a scan output pin for each of the latches in the first cell and the second cell on the schematic; generating a first label on the schematic to provide a first wiring arrangement for the latches in the circuit design, the first wiring arrangement identifies a first order to which the scan input of each of the latches is wired to the scan output of another one of the latches; creating a layout representative of the circuit design; generating a first scan chain having a first length on the layout based on the first wiring arrangement; creating a second scan chain from the first scan chain on the layout, the second scan chain having a second length less than the first length of the first scan chain; and generating a second label on the schematic based on the second scan chain, the second label provides a second wiring arrangement for the latches in the circuit design, the second wiring arrangement identifies a second order to which the scan input of each of the latches is wired to the scan output of another one of the latches.
摘要翻译：提供了一种在电子计算机辅助设计系统中优化电路设计中的扫描链排序的方法。该方法包括：创建具有第一单元和第二单元的电路设计的示意图，第一单元和第二单元各自在其中具有锁存器; 为第一个单元中的每个锁存器和原理图上的第二个单元创建扫描输入引脚和扫描输出引脚; 在原理图上产生第一标签以提供用于电路设计中的锁存器的第一布线布置，第一布线布置识别每个锁存器的扫描输入被连接到另一个的另一个的扫描输出的第一顺序锁存器创建一个代表电路设计的布局; 基于第一布线布置在布局上产生具有第一长度的第一扫描链; 在所述布局上从所述第一扫描链创建第二扫描链，所述第二扫描链具有小于所述第一扫描链的所述第一长度的第二长度; 并且基于所述第二扫描链在所述原理图上产生第二标签，所述第二标签为所述电路设计中的所述锁存器提供第二布线布置，所述第二布线布置识别每个所述闩锁的扫描输入的第二顺序连线到另一个锁存器的扫描输出。

10. 发明申请

US20080320588A1 System of Assigning Permissions to a User by Password 有权
标题翻译：通过密码为用户分配权限的系统
公开(公告)号：US20080320588A1
公开(公告)日：2008-12-25
申请号：US11764842
申请日：2007-06-19
申请人： Daniel Lipetz
发明人： Daniel Lipetz
IPC分类号： H04L9/32
CPC分类号： G06F21/6218 , G06F2221/2141
摘要： A data processing system includes a data storage unit for storing data sets accessible to a user upon receipt of permission. The data processing system restricts access to data sets by requiring a username and then requiring a password to obtain permission for access to a data set stored in a data storage unit. The system is adapted to support use of more than one said password associated with a username; and each of those passwords associated with that username permits a distinct level of access to a particular data set, whereas other passwords can provide different levels of access to any data set assigned thereto.
摘要翻译：数据处理系统包括数据存储单元，用于在接收到许可时存储用户可访问的数据集。数据处理系统通过要求用户名然后需要密码来获得访问存储在数据存储单元中的数据集的权限来限制对数据集的访问。该系统适于支持使用与用户名相关联的多个所述密码; 并且与该用户名相关联的每个密码允许对特定数据集的不同级别的访问，而其他密码可以为分配给其的任何数据集提供不同级别的访问。

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