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1. 发明申请

US20180285582A1 VERIFIABLE KEYED ALL-OR-NOTHING TRANSFORM 审中-公开
公开(公告)号：US20180285582A1
公开(公告)日：2018-10-04
申请号：US15477314
申请日：2017-04-03
申请人： International Business Machines Corporation
发明人： Jason K. Resch , Mark D. Seaborn
IPC分类号： G06F21/62 , H04L9/08 , G06F21/64 , G06F7/72 , G06F21/60
CPC分类号： G06F21/602 , G06F7/72 , H04L9/065 , H04L9/3239 , H04L2209/04 , H04L2209/34
摘要： Systems and methods for encrypting and decrypting data in a dispersed storage network are disclosed. One encryption approach involves generating a random encryption key (REK), producing encrypted data using the REK, determining a computed value (CV) using the encrypted data, and combining the REK, CV and a supplied encryption key (SEK) into an Encrypted Difference (ED). The encrypted data and ED are then combined to produce a secure package. The secure package is then processed by an error coding function and stored as slices. One decryption approach includes accessing the slices and the SEK, decoding the slices to recover the secure package, re-computing the CV from the encrypted data within the secure package, and using the SEK and CV to de-combine the ED and recover the REK. The REK is then used to decrypt the encrypted data. Integrity verification of the secure package may also be used.

2. 发明授权

US09992016B2 Message generation for a cryptographic key generation test 有权
公开(公告)号：US09992016B2
公开(公告)日：2018-06-05
申请号：US15122822
申请日：2015-03-03
申请人： OBERTHUR TECHNOLOGIES
发明人： Alberto Battistello , Christophe Giraud , Guillaume Dabosville , Laurie Genelle
IPC分类号： H04L9/14 , H04L9/08 , H04L9/00 , H04L9/30
CPC分类号： H04L9/08 , G06F7/72 , G06F2207/7204 , H04L9/004 , H04L9/302
摘要： Generation of a message m of order λ(n) for a test of the integrity of the generation of a pair of cryptographic keys within the multiplicative group of integers modulo n=p·q, including: —key pair generation including, to generate p and q: a random selection of candidate integers; and a primality test; —a first search of the multiplicative group of integers modulo p for a generator a; —a second search of the multiplicative group of integers modulo q for a generator b; —a third search for a number y, as message m, verifying: 1≤γ≤n−1, where γ=a mod p and γ=b mod q, the first or second search being performed during the primality test.

3. 发明申请

US20170346632A1 METHOD FOR ON-BOARD PRIME NUMBER GENERATION 审中-公开
公开(公告)号：US20170346632A1
公开(公告)日：2017-11-30
申请号：US15534079
申请日：2015-11-25
申请人： GEMALTO SA
发明人： Charles COULIER , Karine VILLEGAS , Nabil HAMZI , Ali ZEAMARI , Nicolas ROUSSEL
IPC分类号： H04L9/30 , H04L9/08 , G06F7/72 , G06F7/64 , G09C1/00 , G06F7/58
CPC分类号： H04L9/3033 , G06F7/588 , G06F7/64 , G06F7/72 , G06F2207/7204 , G09C1/00 , H04L9/0869
摘要： The present invention relates to a method to generate prime numbers on board a portable device, said method comprising the steps of, each time at least one prime number is requested: when available, retrieve results from previously performed derivation calculation or, if not, select a start point for derivation; process derivation calculation to converge towards a prime number; if a prime number is found, store it and restart derivation calculation from a new start point; stop the derivation calculation after a predetermined amount of time; store intermediate results to be used a next time a prime number will be requested; output a stored prime number.

4. 发明授权

US09577826B2 Method of generating proven prime numbers suitable for being implemented in a smart card 有权
标题翻译：产生适合于在智能卡中实现的已验证素数的方法
公开(公告)号：US09577826B2
公开(公告)日：2017-02-21
申请号：US14365671
申请日：2012-12-12
申请人： INSIDE SECURE
发明人： Benoît Feix , Christophe Clavier , Pascal Paillier , Loïc Thierry
IPC分类号： H04L9/08 , G06F7/58 , G06F7/72 , G06F17/11
CPC分类号： H04L9/0869 , G06F7/58 , G06F7/72 , G06F17/11 , G06F2207/7204 , H04L9/0816 , H04L2209/24
摘要： The invention relates to a method for generating a prime number, implemented in an electronic device, the method including steps of generating a prime number from another prime number using the formula Pr=2P·R+1, where P is a prime number having a number of bits lower than that of the candidate prime number, and R is an integer, and applying the Pocklington primality test to the candidate prime number, the candidate prime number being proven if it passes the Pocklington test. According to the invention, the size in number of bits of the candidate prime number is equal to three times the size of the prime number, to within one unit, the generated candidate prime number being retained as candidate prime number only if the quotient of the integer division of the integer by the prime number is odd.
摘要翻译：本发明涉及一种在电子设备中实现的素数的产生方法，该方法包括以下步骤：使用公式Pr = 2P·R + 1从另一个素数生成素数，其中P是具有比特数低于候选素数，R为整数，并且对候选质数进行Pocklington原语测试，如果候选素数通过Pocklington检验，则验证候选素数。根据本发明，候选素数的比特数的大小等于素数大小的三倍，在一个单位内，所生成的候选素数保留为候选素数，只有当商数整数除以素数的整数除以奇数。

5. 发明授权

US09535656B2 Pipelined modular reduction and division 有权
标题翻译：流水线模块化减排和划分
公开(公告)号：US09535656B2
公开(公告)日：2017-01-03
申请号：US14210966
申请日：2014-03-14
申请人： International Business Machines Corporation
发明人： Vincenzo Condorelli , Silvio Dragone , William Santiago Fernandez , Nihad Hadzic , Andrew R. Ranck
IPC分类号： G06F5/01 , G06F7/72
CPC分类号： G06F5/01 , G06F7/72
摘要： Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.
摘要翻译：实施例涉及模块化减少。一个方面包括执行模块化减少的系统。该系统包括用于存储输入字符串或数字的移位寄存器。该系统还包括以流水线配置布置的多个处理元件，用于将输入串转换成预定义的字母表，或者基于多个模块化减少将该数量转换为不同的基数，多个处理元件之一的输出作为递归分割的一部分，作为流水线中的多个处理元件中的后续处理元件的输入，并且流水线中的多个处理元件中的第一个处理元素的输入是移位寄存器的输出。

6. 发明授权

US09503259B2 System and method for generating and protecting cryptographic keys 有权
标题翻译：用于生成和保护加密密钥的系统和方法
公开(公告)号：US09503259B2
公开(公告)日：2016-11-22
申请号：US14377499
申请日：2012-02-09
申请人： SK MD Mizanur Rahman , James Muir
发明人： SK MD Mizanur Rahman , James Muir
IPC分类号： H04L9/00 , H04L9/08 , G06F7/58 , G06F7/72 , H04L9/30
CPC分类号： H04L9/0869 , G06F7/58 , G06F7/72 , H04L9/0841 , H04L9/3066 , H04L2209/16
摘要： In the present disclosure, implementations of Diffie-Hellman key agreement are provided that, when embodied in software, resist extraction of cryptographically sensitive parameters during software execution by white-box attackers. Four embodiments are taught that make extraction of sensitive parameters difficult during the generation of the public key and the computation of the shared secret. The embodiments utilize transformed random numbers in the derivation of the public key and shared secret. The traditional attack model for Diffie-Hellman implementations considers only black-box attacks, where attackers analyze only the inputs and outputs of the implementation. In contrast, white-box attacks describe a much more powerful type of attacker who has total visibility into the software implementation as it is being executed.
摘要翻译：在本公开中，提供了Diffie-Hellman密钥协议的实现，当以软件体现时，实现了由白盒攻击者在软件执行期间提取加密敏感参数。教导了在公钥生成期间难以提取敏感参数以及计算共享秘密的四个实施例。这些实施例在推导公钥和共享秘密时利用变换后的随机数。 Diffie-Hellman实施的传统攻击模式仅考虑黑匣子攻击，攻击者只分析实施的输入和输出。相比之下，白盒攻击描述了一种更强大的攻击者类型，它们正在执行时对软件实现有全面的了解。

7. 发明授权

US09471276B2 Pipelined modular reduction and division 有权
标题翻译：流水线模块化减排和划分
公开(公告)号：US09471276B2
公开(公告)日：2016-10-18
申请号：US15090908
申请日：2016-04-05
申请人： International Business Machines Corporation
发明人： Vincenzo Condorelli , Silvio Dragone , William Santiago Fernandez , Nihad Hadzic , Andrew R. Ranck
IPC分类号： G06F5/01
CPC分类号： G06F5/01 , G06F7/72
摘要： Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.
摘要翻译：实施例涉及模块化减少。一个方面包括执行模块化减少的系统。该系统包括用于存储输入字符串或数字的移位寄存器。该系统还包括以流水线配置布置的多个处理元件，用于将输入串转换成预定义的字母表，或者基于多个模块化减少将该数量转换为不同的基数，多个处理元件之一的输出作为递归分割的一部分，作为流水线中的多个处理元件中的后续处理元件的输入，并且流水线中的多个处理元件中的第一个处理元素的输入是移位寄存器的输出。

8. 发明授权

US09170771B2 Residue-based error detection for a processor execution unit that supports vector operations 有权
公开(公告)号：US09170771B2
公开(公告)日：2015-10-27
申请号：US14182415
申请日：2014-02-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Maarten Boersma , Juergen Haess
IPC分类号： G06F7/38 , G06F7/483 , G06F7/544 , G06F7/72 , G06F11/10
CPC分类号： G06F7/38 , G06F7/483 , G06F7/5443 , G06F7/72 , G06F11/1008
摘要： A residue generating circuit for an execution unit that supports vector operations includes an operand register and a residue generator coupled to the operand register. The residue generator includes a first residue generation tree coupled to a first section of the operand register and a second residue generation tree coupled to a second section of the operand register. The first residue generation tree is configured to generate a first residue for first data included in the first section of the operand register. The second residue generation tree is configured to generate a second residue for second data included in a second section of the operand register. The first section of the operand register includes a different number of register bits than the second section of the operand register.

9. 发明申请

US20150261499A1 PIPELINED MODULAR REDUCTION AND DIVISION 有权
标题翻译：管道模块化减少和部分
公开(公告)号：US20150261499A1
公开(公告)日：2015-09-17
申请号：US14210966
申请日：2014-03-14
申请人： International Business Machines Corporation
发明人： Vincenzo Condorelli , Silvio Dragone , William Santiago Fernandez , Nihad Hadzic , Andrew R. Ranck
IPC分类号： G06F5/01
CPC分类号： G06F5/01 , G06F7/72
摘要： Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.
摘要翻译：实施例涉及模块化减少。一个方面包括执行模块化减少的系统。该系统包括用于存储输入字符串或数字的移位寄存器。该系统还包括以流水线配置布置的多个处理元件，用于将输入串转换成预定义的字母表，或者基于多个模块化减少将该数量转换为不同的基数，多个处理元件之一的输出作为递归分割的一部分，作为流水线中的多个处理元件中的后续处理元件的输入，并且流水线中的多个处理元件中的第一个处理元素的输入是移位寄存器的输出。

10. 发明授权

US09110768B2 Residue based error detection for integer and floating point execution units 有权
标题翻译：用于整数和浮点执行单元的基于残差的错误检测
公开(公告)号：US09110768B2
公开(公告)日：2015-08-18
申请号：US13730008
申请日：2012-12-28
申请人： INTEL CORPORATION
发明人： Sorin Iacobovici
IPC分类号： G06F11/10 , G06F7/72
CPC分类号： G06F7/72 , G06F7/483 , G06F11/085
摘要： An error detection unit including one or more register files that store at least one operand and at least one operand residue, an operand multiplexor operable to receive the operand, a residue multiplexor operable to receive the operand residue, a source operand residue generator operable to generate at least one generated residue from the operand, a first comparator that compares the operand residue to the generated residue, the result of the first comparator being sent to a reorder buffer, an execution unit that supplies the operand to a residue calculator and a result residue generator, wherein the residue calculator operable to determine an expected residue and the result residue generator operable to generate a result residue, and a second comparator that compares the expected residue with the result residue, the result of the second comparator being sent to the reorder buffer.
摘要翻译：一种错误检测单元，包括存储至少一个操作数和至少一个操作数残差的一个或多个寄存器文件，可操作以接收操作数的操作数多路复用器，可操作以接收操作数残差的残余多路复用器，可操作以产生来自操作数的至少一个产生的残差，将操作数残差与所生成的残差进行比较的第一比较器，将第一比较器的结果发送到重排序缓冲器，将操作数提供给残差计算器的执行单元和结果残差发生器，其中所述残差计算器可操作以确定预期残留，并且所述结果残留发生器可操作以产生结果残留;以及第二比较器，将所述预期残差与所述结果残差进行比较，所述第二比较器的结果被发送到所述重排序缓冲器。

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