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1. 发明授权

US08345522B1 Flexible optical write strategy 有权
标题翻译：灵活的光写策略
公开(公告)号：US08345522B1
公开(公告)日：2013-01-01
申请号：US13405818
申请日：2012-02-27
申请人： Pantas Sutardja , Yingxuan Li , Daniel Mumford
发明人： Pantas Sutardja , Yingxuan Li , Daniel Mumford
IPC分类号： G11B7/00
CPC分类号： G11B7/126 , G11B7/0062
摘要： A method of controlling a laser driver includes determining a set of timing parameters in response to contents of a received bit stream. The method further includes creating a plurality of sets of pulse defining parameters in response to the set of timing parameters, and generating a plurality of generic pulses in response to the plurality of sets of pulse defining parameters. The method also includes combining the plurality of generic pulses into a plurality of enable signals, and creating a plurality of adapted enable signals by selectively replacing one of the plurality of enable signals with an alternative signal. The method further includes outputting the plurality of adapted enable signals to the laser driver.
摘要翻译：控制激光驱动器的方法包括响应于接收到的比特流的内容来确定一组定时参数。该方法还包括响应于该组定时参数创建多组脉冲定义参数，以及响应于多组脉冲定义参数而生成多个通用脉冲。该方法还包括将多个通用脉冲组合成多个使能信号，以及通过用替代信号选择性地替换多个使能信号中的一个来创建多个适配的使能信号。该方法还包括将多个适配的使能信号输出到激光驱动器。

2. 发明授权

US07773479B1 Flexible optical write strategy 有权
标题翻译：灵活的光写策略
公开(公告)号：US07773479B1
公开(公告)日：2010-08-10
申请号：US11455533
申请日：2006-06-19
申请人： Pantas Sutardja , Yingxuan Li , Daniel Mumford
发明人： Pantas Sutardja , Yingxuan Li , Daniel Mumford
IPC分类号： G11B7/00
CPC分类号： G11B7/126 , G11B7/0062
摘要： A driver control module comprises a parameter generation module, a timing encoding module, and a pulse generation module. The parameter generation module receives a bit stream and generates a set of timing parameters based upon contents of the bit stream. The timing encoding module receives the set of timing parameters from the parameter generation module and creates N sets of pulse defining parameters, wherein N is an integer greater than one. The pulse generation module creates N generic pulses using the sets of pulse defining parameters, combines the generic pulses into P enable signals, and outputs the enable signals to a laser driver, wherein P is an integer greater than one.
摘要翻译：驱动器控制模块包括参数产生模块，定时编码模块和脉冲发生模块。参数生成模块基于位流的内容接收比特流并生成一组定时参数。定时编码模块从参数生成模块接收一组定时参数，并创建N组脉冲定义参数，其中N是大于1的整数。脉冲发生模块使用脉冲定义参数组创建N个通用脉冲，将通用脉冲组合成P个使能信号，并将使能信号输出到激光驱动器，其中P是大于1的整数。

3. 发明授权

US08125870B1 Flexible optical write strategy 有权
标题翻译：灵活的光写策略
公开(公告)号：US08125870B1
公开(公告)日：2012-02-28
申请号：US13019011
申请日：2011-02-01
申请人： Pantas Sutardja , Yingxuan Li , Daniel Mumford
发明人： Pantas Sutardja , Yingxuan Li , Daniel Mumford
IPC分类号： G11B7/00
CPC分类号： G11B7/126 , G11B7/0062
摘要： A driver comprising: a pattern module configured to generate a plurality of timing parameters in response to a received bit stream; a timing module configured to determine a plurality of multi-bit parameters in response to the timing parameters; and a pulse module configured to (i) generate each of a plurality of pulses in response to a different one of the plurality of multi-bit parameters, (ii) generate each of a plurality of enable signals in response to a variable combination of the plurality of pulses, and (iii) output the plurality of enable signals to a laser driver.
摘要翻译：一种驱动器，包括：模式模块，被配置为响应于所接收的比特流生成多个定时参数; 定时模块，被配置为响应于所述定时参数确定多个多位参数; 以及脉冲模块，其被配置为（i）响应于所述多个多位参数中的不同的一个参数来产生多个脉冲中的每一个;（ii）响应于所述多位参数的可变组合而产生多个使能信号中的每一个多个脉冲，以及（iii）将多个使能信号输出到激光驱动器。

4. 发明授权

US08082485B1 Method and apparatus for detecting Viterbi decoder errors due to quasi-catastrophic sequences 有权
标题翻译：用于检测由于准灾难性序列引起的维特比解码器错误的方法和装置
公开(公告)号：US08082485B1
公开(公告)日：2011-12-20
申请号：US12156036
申请日：2008-05-29
申请人： Mats Oberg , Daniel Mumford
发明人： Mats Oberg , Daniel Mumford
IPC分类号： H03M13/00
CPC分类号： H03M13/6331 , H03M13/3738 , H03M13/4161
摘要： A Viterbi decoder includes a decision generator configured to generate a full decision output. An error detector is configured to detect errors in the full decision output and generate a signal when the full decision output errors are detected.
摘要翻译：维特比解码器包括被配置为产生完全决策输出的决策发生器。错误检测器被配置为检测完整决策输出中的错误，并且当检测到完全判定输出错误时产生信号。

5. 发明授权

US07383489B1 Method and apparatus for detecting viterbi decoder errors due to quasi-catastrophic sequences 有权
标题翻译：用于检测由于准灾难性序列引起的维特比解码器错误的方法和装置
公开(公告)号：US07383489B1
公开(公告)日：2008-06-03
申请号：US11516364
申请日：2006-09-06
申请人： Mats Oberg , Daniel Mumford
发明人： Mats Oberg , Daniel Mumford
IPC分类号： H03M13/03
CPC分类号： H03M13/6331 , H03M13/3738 , H03M13/4161
摘要： A Viterbi decoder that identifies errors in a full decision output comprises a full decision generator that generates the full decision output. An error detector detects errors in the full decision output and generates a signal when the full decision output errors are detected.
摘要翻译：识别完整决策输出中的错误的维特比解码器包括产生完全决策输出的完全决策生成器。错误检测器检测完整决策输出中的错误，并在检测到完全判定输出错误时产生信号。

6. 发明授权

US07383488B1 Method and apparatus for detecting Viterbi decoder errors due to quasi-catastrophic sequences 有权
标题翻译：用于检测由于准灾难性序列引起的维特比解码器错误的方法和装置
公开(公告)号：US07383488B1
公开(公告)日：2008-06-03
申请号：US11516272
申请日：2006-09-06
申请人： Mats Oberg , Daniel Mumford
发明人： Mats Oberg , Daniel Mumford
IPC分类号： H03M13/03
CPC分类号： H03M13/6331 , H03M13/3738 , H03M13/4161
摘要： A Viterbi decoder that identifies errors in an early decision output comprises an early decision generator that generates the early decision output. An error detector detects errors in the early decision output and generates a signal when the early decision output errors are detected.
摘要翻译：识别早期决策输出中的错误的维特比解码器包括产生早期决策输出的早期决策生成器。误差检测器检测早期判决输出中的错误，并在检测到早期判决输出错误时产生信号。

7. 发明授权

US08046670B1 Method and apparatus for detecting viterbi decoder errors due to quasi-catastrophic sequences 有权
标题翻译：用于检测由于准灾难性序列引起的维特比解码器错误的方法和装置
公开(公告)号：US08046670B1
公开(公告)日：2011-10-25
申请号：US12156040
申请日：2008-05-29
申请人： Mats Oberg , Daniel Mumford
发明人： Mats Oberg , Daniel Mumford
IPC分类号： H03M13/00
CPC分类号： H03M13/6331 , H03M13/3738 , H03M13/4161
摘要： A Viterbi decoder includes an early decision generator that generates an early decision output. An error detector detects errors in the early decision output and generates a signal when the early decision output errors are detected.
摘要翻译：维特比解码器包括产生早期决策输出的早期决策发生器。误差检测器检测早期判决输出中的错误，并在检测到早期判决输出错误时产生信号。

8. 发明授权

US07881172B1 Flexible optical write strategy 有权
标题翻译：灵活的光写策略
公开(公告)号：US07881172B1
公开(公告)日：2011-02-01
申请号：US12853337
申请日：2010-08-10
申请人： Pantas Sutardja , Yingxuan Li , Daniel Mumford
发明人： Pantas Sutardja , Yingxuan Li , Daniel Mumford
IPC分类号： G11B7/00
CPC分类号： G11B7/126 , G11B7/0062
摘要： A driver includes a parameter generation module configured to generate timing parameters based upon a received bit stream. A timing encoding module is configured to determine a plurality of pulse defining parameters based on the timing parameters. A pulse generation module is configured to determine a plurality of generic pulses based on the plurality of pulse defining parameters. The pulse generation module is configured to combine the plurality of generic pulses into a plurality of enable signals. The pulse generation module is configured to selectively invert a first enable signal of the plurality of enable signals. The pulse generation module is configured to output the plurality of enable signals including the first enable signal to a laser driver.
摘要翻译：驱动器包括被配置为基于接收到的比特流来生成定时参数的参数生成模块。定时编码模块被配置为基于定时参数确定多个脉冲定义参数。脉冲发生模块被配置为基于多个脉冲定义参数来确定多个通用脉冲。脉冲发生模块被配置为将多个通用脉冲组合成多个使能信号。脉冲发生模块被配置为选择性地反转多个使能信号的第一使能信号。脉冲发生模块被配置为向激光驱动器输出包括第一使能信号的多个使能信号。

9. 发明授权

US07107514B1 Method and apparatus for detecting Viterbi decoder errors due to quasi-catastophic sequences 有权
标题翻译：用于检测由准准灾难序列引起的维特比解码器错误的方法和装置
公开(公告)号：US07107514B1
公开(公告)日：2006-09-12
申请号：US10393640
申请日：2003-03-21
申请人： Mats Oberg , Daniel Mumford
发明人： Mats Oberg , Daniel Mumford
IPC分类号： H03M13/03
CPC分类号： H03M13/6331 , H03M13/3738 , H03M13/4161
摘要： A Viterbi decoder identifies errors in an early decision output and includes an early decision generator that generates the early decision output. A full decision generator generates a full decision output. An error detector detects errors in the early decision output and generates a disable signal. A secondary early decision generator generates a secondary early decision output. The error detector includes a comparing circuit that disables a prior early decision output if the secondary early decision output is different than the prior early decision output. Alternately, a best path flag generator generates a best path flag when the Viterbi decoder identifies two best paths having the same path metric. A comparing circuit disables the early decision output if a prior secondary early decision output is different than the early decision output, the best path flag is true and a prior best path flag is true.
摘要翻译：维特比解码器识别早期决策输出中的错误，并且包括产生早期决策输出的早期决策生成器。完全决策生成器生成完整的决策输出。误差检测器检测早期判决输出中的错误并产生禁用信号。二次早期决策发生器产生二次早期决策输出。误差检测器包括比较电路，如果二次早期判定输出不同于先前的早期判定输出，则该比较电路禁用先前的早期判定输出。或者，当维特比解码器识别具有相同路径度量的两个最佳路径时，最佳路径标志发生器产生最佳路径标志。如果先前的次级早期决策输出不同于早期决策输出，则比较电路禁用早期决策输出，最佳路径标志为真，并且先前的最佳路径标志为真。

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