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1. 发明授权

US07383488B1 Method and apparatus for detecting Viterbi decoder errors due to quasi-catastrophic sequences 有权
标题翻译：用于检测由于准灾难性序列引起的维特比解码器错误的方法和装置
公开(公告)号：US07383488B1
公开(公告)日：2008-06-03
申请号：US11516272
申请日：2006-09-06
申请人： Mats Oberg , Daniel Mumford
发明人： Mats Oberg , Daniel Mumford
IPC分类号： H03M13/03
CPC分类号： H03M13/6331 , H03M13/3738 , H03M13/4161
摘要： A Viterbi decoder that identifies errors in an early decision output comprises an early decision generator that generates the early decision output. An error detector detects errors in the early decision output and generates a signal when the early decision output errors are detected.
摘要翻译：识别早期决策输出中的错误的维特比解码器包括产生早期决策输出的早期决策生成器。误差检测器检测早期判决输出中的错误，并在检测到早期判决输出错误时产生信号。

2. 发明授权

US08082485B1 Method and apparatus for detecting Viterbi decoder errors due to quasi-catastrophic sequences 有权
标题翻译：用于检测由于准灾难性序列引起的维特比解码器错误的方法和装置
公开(公告)号：US08082485B1
公开(公告)日：2011-12-20
申请号：US12156036
申请日：2008-05-29
申请人： Mats Oberg , Daniel Mumford
发明人： Mats Oberg , Daniel Mumford
IPC分类号： H03M13/00
CPC分类号： H03M13/6331 , H03M13/3738 , H03M13/4161
摘要： A Viterbi decoder includes a decision generator configured to generate a full decision output. An error detector is configured to detect errors in the full decision output and generate a signal when the full decision output errors are detected.
摘要翻译：维特比解码器包括被配置为产生完全决策输出的决策发生器。错误检测器被配置为检测完整决策输出中的错误，并且当检测到完全判定输出错误时产生信号。

3. 发明授权

US07383489B1 Method and apparatus for detecting viterbi decoder errors due to quasi-catastrophic sequences 有权
标题翻译：用于检测由于准灾难性序列引起的维特比解码器错误的方法和装置
公开(公告)号：US07383489B1
公开(公告)日：2008-06-03
申请号：US11516364
申请日：2006-09-06
申请人： Mats Oberg , Daniel Mumford
发明人： Mats Oberg , Daniel Mumford
IPC分类号： H03M13/03
CPC分类号： H03M13/6331 , H03M13/3738 , H03M13/4161
摘要： A Viterbi decoder that identifies errors in a full decision output comprises a full decision generator that generates the full decision output. An error detector detects errors in the full decision output and generates a signal when the full decision output errors are detected.
摘要翻译：识别完整决策输出中的错误的维特比解码器包括产生完全决策输出的完全决策生成器。错误检测器检测完整决策输出中的错误，并在检测到完全判定输出错误时产生信号。

4. 发明授权

US08046670B1 Method and apparatus for detecting viterbi decoder errors due to quasi-catastrophic sequences 有权
标题翻译：用于检测由于准灾难性序列引起的维特比解码器错误的方法和装置
公开(公告)号：US08046670B1
公开(公告)日：2011-10-25
申请号：US12156040
申请日：2008-05-29
申请人： Mats Oberg , Daniel Mumford
发明人： Mats Oberg , Daniel Mumford
IPC分类号： H03M13/00
CPC分类号： H03M13/6331 , H03M13/3738 , H03M13/4161
摘要： A Viterbi decoder includes an early decision generator that generates an early decision output. An error detector detects errors in the early decision output and generates a signal when the early decision output errors are detected.
摘要翻译：维特比解码器包括产生早期决策输出的早期决策发生器。误差检测器检测早期判决输出中的错误，并在检测到早期判决输出错误时产生信号。

5. 发明授权

US07107514B1 Method and apparatus for detecting Viterbi decoder errors due to quasi-catastophic sequences 有权
标题翻译：用于检测由准准灾难序列引起的维特比解码器错误的方法和装置
公开(公告)号：US07107514B1
公开(公告)日：2006-09-12
申请号：US10393640
申请日：2003-03-21
申请人： Mats Oberg , Daniel Mumford
发明人： Mats Oberg , Daniel Mumford
IPC分类号： H03M13/03
CPC分类号： H03M13/6331 , H03M13/3738 , H03M13/4161
摘要： A Viterbi decoder identifies errors in an early decision output and includes an early decision generator that generates the early decision output. A full decision generator generates a full decision output. An error detector detects errors in the early decision output and generates a disable signal. A secondary early decision generator generates a secondary early decision output. The error detector includes a comparing circuit that disables a prior early decision output if the secondary early decision output is different than the prior early decision output. Alternately, a best path flag generator generates a best path flag when the Viterbi decoder identifies two best paths having the same path metric. A comparing circuit disables the early decision output if a prior secondary early decision output is different than the early decision output, the best path flag is true and a prior best path flag is true.
摘要翻译：维特比解码器识别早期决策输出中的错误，并且包括产生早期决策输出的早期决策生成器。完全决策生成器生成完整的决策输出。误差检测器检测早期判决输出中的错误并产生禁用信号。二次早期决策发生器产生二次早期决策输出。误差检测器包括比较电路，如果二次早期判定输出不同于先前的早期判定输出，则该比较电路禁用先前的早期判定输出。或者，当维特比解码器识别具有相同路径度量的两个最佳路径时，最佳路径标志发生器产生最佳路径标志。如果先前的次级早期决策输出不同于早期决策输出，则比较电路禁用早期决策输出，最佳路径标志为真，并且先前的最佳路径标志为真。

6. 发明授权

US08836387B1 Methods and systems for reducing jitter 有权
标题翻译：减少抖动的方法和系统
公开(公告)号：US08836387B1
公开(公告)日：2014-09-16
申请号：US12984356
申请日：2011-01-04
申请人： Jin Xie , Bin Ni , Mats Oberg
发明人： Jin Xie , Bin Ni , Mats Oberg
IPC分类号： H03L7/06
CPC分类号： H03L7/093
摘要： Methods and systems for compensating reducing jitter produced by a phase-locked loop are disclosed. For example, in a particular embodiment, a phase-locked loop device for reducing jitter may include a voltage-control oscillator (VCO) signal configured to produce a VCO signal, phase-detection circuitry configured to compare an input signal and the VCO signal to produce a phase error signal, and slew-rate limiting circuitry configured to receive the phase error signal and apply a slew-rate limit process on the phase error signal to produce a modified error signal.
摘要翻译：公开了用于补偿由锁相环产生的抖动的方法和系统。例如，在特定实施例中，用于减少抖动的锁相环装置可以包括被配置为产生VCO信号的电压控制振荡器（VCO）信号，相位检测电路被配置为将输入信号和VCO信号进行比较产生相位误差信号和摆率限制电路，其配置为接收相位误差信号，并对相位误差信号施加转换速率限制处理以产生修正的误差信号。

7. 发明申请

US20130047055A1 ERROR CORRECTION CODE TECHNIQUES FOR MATRICES WITH INTERLEAVED CODEWORDS 失效
标题翻译：错误校正代码技术用于具有互换代码的矩阵
公开(公告)号：US20130047055A1
公开(公告)日：2013-02-21
申请号：US13556466
申请日：2012-07-24
申请人： Mats Oberg , Jin Xie
发明人： Mats Oberg , Jin Xie
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11B20/1833 , G11B20/1866 , G11B2020/1846 , H03M13/2954
摘要： A decoding system includes a decoder, a first module and a second module. The decoder is configured to receive data read from an optical storage medium and perform a first decoding iteration and a second decoding iteration to decode the data. The first decoding iteration includes generating a resultant matrix. The first module is configured to, based on first decoding statuses of multiple bytes in the resultant matrix, determine second decoding statuses of bytes proximate to failed bytes of a feedback matrix. The feedback matrix is generated based on the resultant matrix. The first module is configured to mark selected ones of the failed bytes as erasures based on the second decoding statuses. The second module is configured to correct one or more of the bytes marked as erasures during the second decoding iteration.
摘要翻译：解码系统包括解码器，第一模块和第二模块。解码器被配置为接收从光学存储介质读取的数据，并执行第一解码迭代和第二解码迭代以解码数据。第一解码迭代包括生成合成矩阵。第一模块被配置为基于所得到的矩阵中的多个字节的第一解码状态来确定接近反馈矩阵的失败字节的字节的第二解码状态。基于得到的矩阵生成反馈矩阵。第一模块被配置为基于第二解码状态将所选出的故障字节标记为擦除。第二模块被配置为校正在第二解码迭代期间标记为擦除的一个或多个字节。

8. 发明授权

US08305703B2 Method and apparatus for determining a location of a defect on a storage medium 有权
标题翻译：用于确定存储介质上的缺陷的位置的方法和装置
公开(公告)号：US08305703B2
公开(公告)日：2012-11-06
申请号：US13189111
申请日：2011-07-22
申请人： Mats Oberg
发明人： Mats Oberg
IPC分类号： G11B5/09
CPC分类号： G11B7/0948 , G11B20/1883 , G11B2220/20
摘要： A defect is detected on a storage medium of a disk drive. A location of the defect is determined, within a smallest addressable unit of data stored on the storage medium. An indication of the location is stored in a memory. A location of a sensor of the disk drive relative to the data stored on the storage medium is monitored. A response of at least one of a defect detector of the disk drive, a read channel controller of the disk drive, and a servo controller of the disk drive is changed based on the location of the sensor relative to the data stored on the storage medium and the stored indication of the location of the defect.
摘要翻译：在磁盘驱动器的存储介质上检测到缺陷。在存储在存储介质上的数据的最小可寻址单元内确定缺陷的位置。位置的指示存储在存储器中。监视磁盘驱动器的传感器相对于存储在存储介质上的数据的位置。基于传感器相对于存储在存储介质上的数据的位置来改变盘驱动器的缺陷检测器，盘驱动器的读通道控制器和盘驱动器的伺服控制器中的至少一个的响应以及存储的缺陷位置的指示。

9. 发明授权

US08102740B1 Offset loop for wobble 有权
标题翻译：偏移回路用于摆动
公开(公告)号：US08102740B1
公开(公告)日：2012-01-24
申请号：US12896358
申请日：2010-10-01
申请人： Mats Oberg , Jingfeng Liu
发明人： Mats Oberg , Jingfeng Liu
IPC分类号： G11B20/10
CPC分类号： G11B20/1403 , G11B7/0053 , G11B7/094 , G11B20/1217 , G11B2020/1239 , G11B2020/1274 , G11B2020/1287 , G11B2220/2537
摘要： An automated capability is provided in which an offset correction is automatically determined and routinely updated in order to reduce or otherwise eliminate data retrieval errors that may be caused by low level distortion in optical disc data storage recording, re-recording and retrieval system. The capability is implemented through an improved offset control loop for reading information from a modulated wobble signal with which the data is recorded to an optical disc data storage medium to provide detection of an offset and correction of that offset to facilitate implementation of precise timing synchronization and/or encoded information contact in the system. The offset detector measures a wobble signal and mathematically converts detected information regarding the measured wobble signal to an offset correction by integrating the wobble signal over a specific time interval and comparing the integrated value to an expected integrated value. The integration may be performed over at least one period of the sinusoidal wobble signal, and the correction added to the wobble signal.
摘要翻译：提供了一种自动化能力，其中自动确定和定期更新偏移校正，以便减少或以其他方式消除可能由光盘数据存储记录，重新记录和检索系统中的低电平失真引起的数据检索错误。该能力通过改进的偏移控制环路实现，用于从调制的摆动信号读取信息，将数据记录到调制摆动信号到光盘数据存储介质，以提供偏移的检测和该偏移的校正，以便于实现精确的定时同步， /或编码信息联系在系统中。偏移检测器测量摆动信号，并通过在特定时间间隔上积分摆动信号并将积分值与预期积分值进行比较，将关于测量的摆动信号的检测信息数学转换为偏移校正。可以在正弦摆动信号的至少一个周期上执行积分，并且将校正添加到摆动信号。

10. 发明授权

US08031573B1 Supplementary timing recovery 有权
标题翻译：补充时间恢复
公开(公告)号：US08031573B1
公开(公告)日：2011-10-04
申请号：US12767393
申请日：2010-04-26
申请人： Jin Xie , Mats Oberg
发明人： Jin Xie , Mats Oberg
IPC分类号： G11B7/0045
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10222 , G11B20/1024 , G11B20/10444 , G11B20/10462 , G11B20/14 , G11B2220/2537
摘要： Aspects of the disclosure provide a signal processing circuit to reconstruct data from an analog signal. The signal processing circuit includes an analog to digital converter (ADC), an equalizer, a first timing compensation module, a phase-shift module and a second timing compensation module. The ADC receives an analog input signal, samples the analog input signal based on a sampling clock signal, and converts the sampled analog input signal into a digital output signal. The equalizer equalizes the digital output signal. The first timing compensation module detects a first timing error based on the digital output signal, and adjusts the sampling clock signal based on the first timing error. The phase-shift module phase-shifts the equalized digital output signal based on a phase-shift signal. The second timing compensation module detects a second timing error based on the equalized digital output signal, and adjusts the phase-shift signal based on the second timing error.
摘要翻译：本公开的方面提供了一种用于从模拟信号重构数据的信号处理电路。信号处理电路包括模数转换器（ADC），均衡器，第一定时补偿模块，相移模块和第二定时补偿模块。 ADC接收模拟输入信号，根据采样时钟信号采样模拟输入信号，并将采样的模拟输入信号转换为数字输出信号。均衡器使数字输出信号均衡。第一定时补偿模块基于数字输出信号检测第一定时误差，并且基于第一定时误差来调整采样时钟信号。相移模块基于相移信号对均衡的数字输出信号进行相移。第二定时补偿模块基于均衡的数字输出信号检测第二定时误差，并且基于第二定时误差来调整相移信号。

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