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1. 发明授权

US09511453B2 Solder paste composition, a solder paste and a soldering flux 有权
标题翻译：焊膏组合物，焊膏和焊剂
公开(公告)号：US09511453B2
公开(公告)日：2016-12-06
申请号：US13530751
申请日：2012-06-22
申请人： Huiying Yang , Daoqiang Lu
发明人： Huiying Yang , Daoqiang Lu
IPC分类号： B23K35/36 , B23K35/26 , B23K35/362
CPC分类号： B23K35/3601 , B23K35/262 , B23K35/3613 , B23K35/3618 , B23K35/362
摘要： The present invention relates to a solder paste composition, a solder paste and a soldering flux. The soldering flux comprises a resin, a thixotropic agent, an activator, a solvent as well as a long-chain thiol and/or an organic chelating agent.
摘要翻译：本发明涉及一种焊膏组合物，焊膏和焊剂。焊剂包括树脂，触变剂，活化剂，溶剂以及长链硫醇和/或有机螯合剂。

2. 发明授权

US08230589B2 Method of mounting an optical device 有权
标题翻译：安装光学装置的方法
公开(公告)号：US08230589B2
公开(公告)日：2012-07-31
申请号：US12054777
申请日：2008-03-25
申请人： Daoqiang Lu , Johanna Swan , Henning Braunisch
发明人： Daoqiang Lu , Johanna Swan , Henning Braunisch
IPC分类号： H05K3/34
CPC分类号： H01S5/0261 , H01L24/13 , H01L24/16 , H01L25/16 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49165 , H01L2924/00012 , H01L2924/00
摘要： A method for aligning at least two photonic components over an interposer, and an optical package that may align such components. The method may include providing an interposer; fabricating electrical conductors passing from one surface of the interposer to an opposite surface of the interposer at selected contact positions; soldering the photonic components over the selected contact positions on the first surface, while allowing solder self-alignment. Other embodiments are described and claimed.
摘要翻译：一种用于使插入器上的至少两个光子分量对准的方法，以及可以对准这些部件的光学封装。该方法可以包括提供插入器; 制造从所述插入件的一个表面到选定的接触位置处的所述插入件的相对表面的电导体; 将光子组件焊接在第一表面上所选择的接触位置上，同时允许焊料自对准。描述和要求保护其他实施例。

3. 发明授权

US07980865B2 Substrate with raised edge pads 有权
标题翻译：基片与凸起的边缘垫
公开(公告)号：US07980865B2
公开(公告)日：2011-07-19
申请号：US11315854
申请日：2005-12-22
申请人： Wei Shi , Daoqiang Lu , Qing Zhou , Jiangqi He
发明人： Wei Shi , Daoqiang Lu , Qing Zhou , Jiangqi He
IPC分类号： H01R12/00
CPC分类号： H05K7/1061 , Y10T29/49117
摘要： A separable electrical connection may be provided with a landside pad on one of two electrical components to be joined. The landside pad may be made up of two parts, including a flat portion and a raised edge formed on the flat portion. In some embodiments, the raised edge may have a closed geometric shape. Then, a socket contact engaging the junction between the flat portion and the raised edge is prevented from sliding off of the landside pad by the raised edge. In addition, dual areas of electrical connection can be established between both the flat portion and raised edge of the landside pad and the correspondingly shaped pair of portions on the socket. This increases the electrical efficiency of the connection and its security.
摘要翻译：可分离的电连接可以在待连接的两个电气部件之一上设置有陆侧焊盘。侧面垫可以由两部分组成，包括平坦部分和形成在平坦部分上的凸起边缘。在一些实施例中，凸起边缘可以具有闭合的几何形状。然后，通过凸起边缘防止接合平坦部分和凸起边缘之间的连接处的插座触点从边缘垫片滑出。此外，可以在陆侧衬垫的平坦部分和凸起边缘以及插座上的相应形状的一对部分之间建立双重电连接区域。这增加了连接的电效率及其安全性。

4. 发明授权

US07767486B2 High-volume on-wafer heterogeneous packaging of optical interconnects 有权
标题翻译：光互连的大容量片上异构封装
公开(公告)号：US07767486B2
公开(公告)日：2010-08-03
申请号：US11943973
申请日：2007-11-21
申请人： Mohammed Edris , Daoqiang Lu
发明人： Mohammed Edris , Daoqiang Lu
IPC分类号： H01L33/00 , H01L31/0203
CPC分类号： G02B6/4249 , G02B6/4292 , H01L21/565 , H01L23/544 , H01L24/81 , H01L24/96 , H01L25/16 , H01L31/12 , H01L2223/54426 , H01L2224/81136 , H01L2224/81801 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/10158 , H01L2924/10329 , H01L2924/10336 , H01L2924/12043 , H01L2924/14 , H01L2924/1461 , H01L2924/19043 , H01L2924/00
摘要： An optical connector module complete with optoelectronic devices, supporting integrated circuitry, and connector housing may be fabricated on a wafer level. A plurality of cavities may be formed on the backside of the wafer to accommodate an optoelectronic device. Active circuitry may be formed in a front side of the wafer. Through-vias electrically connect the front side to the back side. The backside of the wafer is overmolded with a polymer layer which when singulated into individual dies forms the plastic housing of an optical connector module.
摘要翻译：具有光电器件，支持集成电路和连接器外壳的光学连接器模块可以在晶片级上制造。可以在晶片的背面上形成多个空腔以容纳光电器件。有源电路可以形成在晶片的前侧。通孔将前侧电连接到背面。晶片的背面用聚合物层包覆成型，当聚合物层分成单独的模具形成光学连接器模块的塑料外壳时。

5. 发明授权

US07703991B2 Flip-chip mountable optical connector for chip-to-chip optical interconnectability 失效
标题翻译：用于芯片到芯片光学互连的倒装芯片安装光学连接器
公开(公告)号：US07703991B2
公开(公告)日：2010-04-27
申请号：US11124033
申请日：2005-05-06
申请人： Daoqiang Lu , Gilroy J. Vandentop , Henning Braunisch
发明人： Daoqiang Lu , Gilroy J. Vandentop , Henning Braunisch
IPC分类号： G02B6/36
CPC分类号： G02B6/4232 , G02B6/4214 , G02B6/4292 , G02B6/43 , H01L2224/16225 , H05K1/0274 , H05K3/3436
摘要： An optical connector comprises a housing having a cavity extending there through to accept a mating connector. The connector comprises no optical components. Dummy solder bonding pads positioned on the connector allow the connector to be automated flip-chip bonded over a substrate waveguide.
摘要翻译：光学连接器包括壳体，该壳体具有在其上延伸以容纳匹配连接器的空腔。连接器不包括光学部件。定位在连接器上的虚拟焊接焊盘允许连接器在衬底波导上自动倒装芯片结合。

6. 发明授权

US07675182B2 Die warpage control 有权
标题翻译：模翘曲控制
公开(公告)号：US07675182B2
公开(公告)日：2010-03-09
申请号：US11862844
申请日：2007-09-27
申请人： Hai Xiao Sun , Daoqiang Lu
发明人： Hai Xiao Sun , Daoqiang Lu
IPC分类号： H01L23/29
CPC分类号： H01L23/3157 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2224/274 , H01L2224/29101 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2224/8385 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/3511 , H01L2924/00 , H01L2924/01013 , H01L2924/01028 , H01L2924/01014 , H01L2924/01025 , H01L2924/01026 , H01L2924/01022 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package comprises a substrate; a semiconductor die that comprises a set of one or more interconnects on one side to couple to the substrate; and a shape memory alloy layer provided on another side of the semiconductor die to compensate warpage of the semiconductor die. The shape memory alloy layer deforms with warpage of the semiconductor die and changes from the deformed shape to an original shape to flatten the semiconductor die in response to rise of a temperature during coupling of the die to the substrate.
摘要翻译：半导体封装包括衬底; 半导体管芯，其包括在一侧上的一组或多个互连件以耦合到所述衬底; 以及设置在半导体管芯的另一侧的形状记忆合金层，以补偿半导体管芯的翘曲。形状记忆合金层随着半导体管芯的翘曲而变形，并且从变形形状变为原始形状，以在管芯与衬底的耦合期间响应于温度升高而平坦化半导体管芯。

7. 发明授权

US07626251B2 Microelectronic die assembly having thermally conductive element at a backside thereof and method of making same 有权
标题翻译：在其背面具有导热元件的微电子模具组件及其制造方法
公开(公告)号：US07626251B2
公开(公告)日：2009-12-01
申请号：US11529851
申请日：2006-09-29
申请人： Daoqiang Lu , Chuan Hu , Dongming He
发明人： Daoqiang Lu , Chuan Hu , Dongming He
IPC分类号： H01L23/10
CPC分类号： H01L23/433 , H01L21/563 , H01L23/3735 , H01L2924/0002 , H01L2924/16152 , H01L2924/00
摘要： A microelectronic die assembly. The die assembly includes a microelectronic die, and a thermally conductive element attached to the backside of the die with a thermal interface material. The thermally conductive element has lateral dimensions smaller than, substantially equal to, or larger than lateral dimensions of the die by up to a maximum amount, wherein the maximum amount is adapted to allow a mounting of the die assembly to a package substrate.
摘要翻译：微电子模组件。模具组件包括微电子管芯和导热元件，其通过热界面材料附接到管芯的背面。导热元件的横向尺寸小于，基本上等于或大于模具的横向尺寸直到最大量，其中最大量适于允许将模具组件安装到封装衬底。

8. 发明授权

US07554203B2 Electronic assembly with stacked IC's using two or more different connection technologies and methods of manufacture 有权
标题翻译：电子组装与堆叠IC使用两种或多种不同的连接技术和制造方法
公开(公告)号：US07554203B2
公开(公告)日：2009-06-30
申请号：US11427917
申请日：2006-06-30
申请人： Qing A Zhou , Daoqiang Lu , Wei Shi , Jiangqi He
发明人： Qing A Zhou , Daoqiang Lu , Wei Shi , Jiangqi He
IPC分类号： H01L29/40
CPC分类号： H01L24/81 , H01L24/17 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/1403 , H01L2224/141 , H01L2224/16145 , H01L2224/1703 , H01L2224/48091 , H01L2224/49171 , H01L2224/4943 , H01L2224/731 , H01L2224/73207 , H01L2224/81194 , H01L2224/81801 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06562 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (“IC”) package having two or more dice stacked on a substrate and electrically coupled using two or more different connection technologies may improve high-speed input/output (“I/O”) bandwidth. In an embodiment, one die is a processor and at least one other die is a dynamic random access memory (“DRAM”). One or more of the dice may be thinned and placed between the substrate and a portion of one or more of the other dice, which may be horizontally offset. One or more of the dice may be embedded in the substrate. The dice may be coupled to each other and to the substrate using a combination of controlled-collapse chip connection (“C4”) and wirebonding connection technologies. Methods of fabrication, and application of the package to an electronic assembly and to an electronic system, are also described.
摘要翻译：具有堆叠在基板上并且使用两个或多个不同连接技术电耦合的两个或多个骰子的集成电路（“IC”）封装可以改善高速输入/输出（“I / O”）带宽。在一个实施例中，一个管芯是处理器，并且至少一个其它管芯是动态随机存取存储器（“DRAM”）。一个或多个骰子可以变薄并且放置在基底和可以水平偏移的另一个骰子中的一个或多个的一部分之间。一个或多个骰子可以嵌入在基底中。骰子可以使用控制崩溃芯片连接（“C4”）和引线键合连接技术的组合彼此耦合到基板。还描述了制造方法以及将包装应用于电子组件和电子系统。

9. 发明申请

US20090162005A1 Wafer based optical interconnect 有权
标题翻译：基于晶圆的光互连
公开(公告)号：US20090162005A1
公开(公告)日：2009-06-25
申请号：US12004541
申请日：2007-12-20
申请人： Daoqiang Lu , Henning Braunisch
发明人： Daoqiang Lu , Henning Braunisch
IPC分类号： G02B6/12 , G02B6/13
CPC分类号： G02B6/4231
摘要： In general, in one aspect, a method includes forming conductive layers on a wafer. A through cavity is formed in alignment with the conductive layers. The through cavity is to permit an optical signal from an optical waveguide within an optical connector to pass therethrough. Alignment holes are formed on each side of the through cavity to receive alignment pins. The wafer having the conductive layers, the through cavity in alignment with the conductive layers, and the alignment holes on each side of the through cavity forms an optical-electrical (O/E) interface. An O/E converter is mounted to the metal layers in alignment with the through cavity. The alignment pins and the alignment holes are used to passively align the optical waveguide and the O/E converter.
摘要翻译：通常，一方面，一种方法包括在晶片上形成导电层。形成与导电层对准的通孔。通孔是允许光连接器内的光波导的光信号通过。对准孔形成在通孔的每一侧以接收对准销。具有导电层的晶片，与导电层对准的通孔和通孔的每一侧上的对准孔形成光电（O / E）界面。 O / E转换器安装到与通孔对准的金属层上。对准引脚和对准孔用于被动对准光波导和O / E转换器。

10. 发明授权

US07534715B2 Methods including fluxless chip attach processes 失效
标题翻译：方法包括无通芯片贴片工艺
公开(公告)号：US07534715B2
公开(公告)日：2009-05-19
申请号：US11323526
申请日：2005-12-29
申请人： Susheel Jadhav , Daoqiang Lu , Nitin Deshpande
发明人： Susheel Jadhav , Daoqiang Lu , Nitin Deshpande
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L24/10 , H01L24/13 , H01L24/75 , H01L24/81 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/13609 , H01L2224/75 , H01L2224/75314 , H01L2224/757 , H01L2224/7598 , H01L2224/81054 , H01L2224/81136 , H01L2224/81193 , H01L2224/81203 , H01L2224/8121 , H01L2224/8181 , H01L2224/81815 , H01L2224/8183 , H01L2224/81907 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2224/29099 , H01L2924/00
摘要： Electronic devices and methods for fabricating electronic devices are described. One method includes providing a plurality of first metal bumps on a first surface, and a plurality of second metal bumps on a second surface, wherein at least one of (i) the plurality of first metal bumps, and (ii) the plurality of second metal bumps, comprises a solder. The method also includes forming a metal region including indium and tin, on at least one of (i) the plurality of first metal bumps, and (ii) the plurality of second metal bumps. The method also includes positioning the first metal bumps on the second metal bumps, and heating the metal bumps and the metal region and melting the solder. Other embodiments are described and claimed.
摘要翻译：描述了用于制造电子设备的电子设备和方法。一种方法包括在第一表面上设置多个第一金属凸块，以及在第二表面上设置多个第二金属凸块，其中，（i）多个第一金属凸块中的至少一个，以及（ii）多个第二金属凸块金属凸块，包括焊料。该方法还包括在（i）多个第一金属凸块和（ii）多个第二金属凸块中的至少一个上形成包括铟和锡的金属区域。该方法还包括将第一金属凸块定位在第二金属凸块上，并加热金属凸块和金属区域并熔化焊料。描述和要求保护其他实施例。

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