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    • 1. 发明授权
    • Measured, allocation of speculative branch instructions to processor execution units
    • 测量,分配给处理器执行单元的推测分支指令
    • US06338133B1
    • 2002-01-08
    • US09267200
    • 1999-03-12
    • David Andrew Schroter
    • David Andrew Schroter
    • G06F938
    • G06F9/3814G06F9/3836G06F9/384G06F9/3842G06F9/3857
    • A method and system for branch dispatching of instructions in a data processor. A processor having one or more buffers for storing instructions and one or more execution units for executing instructions is utilized. Each unit has a corresponding queue which holds instructions pending execution. First, a threshold level (selected maximum number of instructions in the instruction queue) is set. The current utilization measure for one or more execution units in the data processing system is determined. The current utilization measure is compared to the predetermined threshold value; and a speculative branch instruction is dispatched to a selected execution unit when the current utilization measure is less than the predetermined threshold value.
    • 一种用于在数据处理器中分支调度指令的方法和系统。 利用具有用于存储指令的一个或多个缓冲器和用于执行指令的一个或多个执行单元的处理器。 每个单元都有一个对应的队列,其中保存指令等待执行。 首先,设置阈值级别(指令队列中指定的最大指令数)。 确定数据处理系统中的一个或多个执行单元的当前利用措施。 将当前利用度量与预定阈值进行比较; 并且当当前利用度量小于预定阈值时,将推测性分支指令调度到所选择的执行单元。
    • 4. 发明授权
    • System and method cancelling a speculative branch
    • 系统和方法取消推测分支
    • US06792524B1
    • 2004-09-14
    • US09137653
    • 1998-08-20
    • Milford John PetersonDavid Andrew SchroterAlbert James Van Norstrand
    • Milford John PetersonDavid Andrew SchroterAlbert James Van Norstrand
    • G06F944
    • G06F9/3842G06F9/3844
    • For each predicted branch within a processor, an entry is maintained within a branch history table. The entry within the branch history table also includes an indication of the past record for that particular branch instruction, which indicates how correct the branch prediction has been in the past. When the field value associated with the predicted branch exceeds a certain threshold, indicating that the past predictions associated with that branch instruction have been at an unacceptable level, then the speculative branch instructions dispatching is suspended for that particular branch instruction. Alternative embodiments utilize a global indicator for suspending or cancelling instruction dispatch when the frequency of previous incorrect branch predictions increases beyond a preselected threshold.
    • 对于处理器内的每个预测分支,条目保持在分支历史表中。 分支历史表中的条目还包括针对该特定分支指令的过去记录的指示,其指示分支预测在过去如何正确。 当与预测分支相关联的字段值超过某个阈值时,指示与该分支指令相关联的过去预测已经处于不可接受的水平,则针对该特定分支指令暂停推测分支指令分派。 当先前错误分支预测的频率增加超过预选阈值时,替代实施例利用全局指示符来暂停或取消指令分派。
    • 5. 发明授权
    • Data processing system having an apparatus for out-of-order register
operations and method therefor
    • 数据处理系统具有无序寄存器操作的装置及其方法
    • US6061785A
    • 2000-05-09
    • US24804
    • 1998-02-17
    • Kevin Arthur ChiarotA. James Van Norstrand, Jr.David Andrew Schroter
    • Kevin Arthur ChiarotA. James Van Norstrand, Jr.David Andrew Schroter
    • G06F9/305G06F9/32G06F9/38G06F15/00
    • G06F9/30094G06F9/3836G06F9/3838G06F9/384G06F9/3855
    • An apparatus for condition register (CR) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, logical operations on CR operands may be executed out-of-order using the CR renaming mechanism. Any instruction that updates the CR data has an associated instruction identifier (IID) stored in a register. Subsequent condition register logical (LCR) instructions that use data in the CR use the stored IID to determine when the CR data has been updated by the execution of the instruction corresponding to the stored IID. When an instruction causing a CR data value update finishes executing, the updated data is obtained by snooping the finish bus of the corresponding execution unit. In this way, these instructions can obtain CR data prior to completion of the preceding instructions. Because the updated CR data is available to the LCR next to execute before the updating instruction completes, deserialized execution of LCR instructions is thereby realized.
    • 实现了条件寄存器(CR)重命名的装置及其使用方法。 在具有流水线架构的中央处理单元(CPU)中,使用CR重命名机制可以执行对无效操作数的逻辑运算。 更新CR数据的任何指令都具有存储在寄存器中的关联指令标识符(IID)。 使用CR中的数据的后续条件寄存器逻辑(LCR)指令使用存储的IID来确定通过执行与存储的IID相对应的指令来更新CR数据。 当导致CR数据值更新的指令完成执行时,通过窥探相应执行单元的完成总线来获得更新的数据。 以这种方式,这些指令可以在完成前面的指令之前获得CR数据。 因为在更新指令完成之前更新的CR数据可用于下一个执行的LCR,从而实现了反序列化执行LCR指令。
    • 8. 发明授权
    • Processor and method of prefetching data based upon a detected stride
    • 基于检测到的步幅预取数据的处理器和方法
    • US06430680B1
    • 2002-08-06
    • US09052567
    • 1998-03-31
    • William Elton BurkyDavid Andrew SchroterShih-Hsiung Stephen TungMichael Thomas Vaden
    • William Elton BurkyDavid Andrew SchroterShih-Hsiung Stephen TungMichael Thomas Vaden
    • G06F900
    • G06F9/3455G06F9/3832
    • A processor and method of fetching data within a data processing system are disclosed. According to the method, a first difference between a first load address and a second load address is calculated. In addition, a determination is made whether a second difference between a third load address and the second load address is equal to the first difference. In response to a determination that the first difference and the second difference are equal, a fourth load address, which is generated by adding the third address and the second difference, is transmitted to the memory as a memory fetch address. In an embodiment of the data processing system including a processor having an associated cache, the fourth load address is transmitted to the memory only if the fourth load address is not resident in the cache or the target of an outstanding memory fetch request.
    • 公开了一种在数据处理系统内取出数据的处理器和方法。 根据该方法,计算第一加载地址和第二加载地址之间的第一差。 此外,确定第三加载地址和第二加载地址之间的第二差是否等于第一差。 响应于确定第一差异和第二差异相等,通过将第三地址和第二差值相加产生的第四加载地址作为存储器提取地址被发送到存储器。 在包括具有关联高速缓存的处理器的数据处理系统的实施例中,仅当第四加载地址不驻留在高速缓存中或未完成的存储器提取请求的目标时才将第四加载地址发送到存储器。
    • 9. 发明授权
    • Apparatus for software initiated prefetch and method therefor
    • 软件启动预取装置及其方法
    • US06401192B1
    • 2002-06-04
    • US09166435
    • 1998-10-05
    • David Andrew SchroterMichael Thomas Vaden
    • David Andrew SchroterMichael Thomas Vaden
    • G06F900
    • G06F9/383G06F9/30047G06F9/3455G06F12/0862G06F2212/6028
    • A mechanism and method for software hint initiated prefetch is provided. The prefetch may be directed to a prefetch of data for loading into a data cache, instructions for entry into an instruction cache or for either, in an embodiment having a combined cache. In response to a software instruction in an instruction stream, a plurality of prefetch specification data values are loaded into a register having a plurality of entries corresponding thereto. Prefetch specification data values include the address of the first cache line to be prefetched, and the stride, or the incremental offset, of the address of subsequent lines to be prefetched. Prefetch requests are generated by a prefetch control state machine using the prefetch specification data values stored in the register. Prefetch requests are issued to a hierarchy of cache memory devices. If a cache hit occurs having the specified cache coherency, the prefetch is vitiated. Otherwise, the request is passed to system memory for retrieval of the requested cache line.
    • 提供了软件提示启动预取的机制​​和方法。 预取可以被引导到用于加载到数据高速缓存中的数据的预取,用于进入指令高速缓存的指令,或者在具有组合高速缓存的实施例中。 响应于指令流中的软件指令,将多个预取指定数据值加载到具有与其对应的多个条目的寄存器中。 预取指定数据值包括要预取的第一个高速缓存行的地址以及要预取的后续行的地址的步幅或增量偏移量。 预取请求由预取控制状态机使用寄存器中存储的预取指定数据值生成。 预取请求被发布到高速缓存存储器设备的层次结构。 如果发生具有指定高速缓存一致性的高速缓存命中,则预取将被破坏。 否则,请求被传递到系统内存以检索所请求的高速缓存行。