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1. 发明授权

US06275918B1 Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold 失效
标题翻译：从增加访问指示符阈值的数量获取历史表信息中的载入目标操作数预取地址
公开(公告)号：US06275918B1
公开(公告)日：2001-08-14
申请号：US09268307
申请日：1999-03-16
申请人： William Elton Burky , Peter Steven Lenk , Dung Quoc Nguyen , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
发明人： William Elton Burky , Peter Steven Lenk , Dung Quoc Nguyen , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
IPC分类号： G06F934
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832
摘要： A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.
摘要翻译：公开了一种利用预取历史表改善数据处理系统中的预取精度的方法和系统。该方法基于条目中包含的有效位的状态，将指令地址的一部分与位于预取历史表中的条目的地址进行比较。如果有效位被设置并且地址匹配，则检查条目内的指示符字段以查看其是否等于或大于阈值级别。当指示符字段大于阈值电平时，将根据步幅和方向预取目标操作数地址。

2. 发明授权

US06430680B1 Processor and method of prefetching data based upon a detected stride 失效
标题翻译：基于检测到的步幅预取数据的处理器和方法
公开(公告)号：US06430680B1
公开(公告)日：2002-08-06
申请号：US09052567
申请日：1998-03-31
申请人： William Elton Burky , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
发明人： William Elton Burky , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
IPC分类号： G06F900
CPC分类号： G06F9/3455 , G06F9/3832
摘要： A processor and method of fetching data within a data processing system are disclosed. According to the method, a first difference between a first load address and a second load address is calculated. In addition, a determination is made whether a second difference between a third load address and the second load address is equal to the first difference. In response to a determination that the first difference and the second difference are equal, a fourth load address, which is generated by adding the third address and the second difference, is transmitted to the memory as a memory fetch address. In an embodiment of the data processing system including a processor having an associated cache, the fourth load address is transmitted to the memory only if the fourth load address is not resident in the cache or the target of an outstanding memory fetch request.
摘要翻译：公开了一种在数据处理系统内取出数据的处理器和方法。根据该方法，计算第一加载地址和第二加载地址之间的第一差。此外，确定第三加载地址和第二加载地址之间的第二差是否等于第一差。响应于确定第一差异和第二差异相等，通过将第三地址和第二差值相加产生的第四加载地址作为存储器提取地址被发送到存储器。在包括具有关联高速缓存的处理器的数据处理系统的实施例中，仅当第四加载地址不驻留在高速缓存中或未完成的存储器提取请求的目标时才将第四加载地址发送到存储器。

3. 发明授权

US06401192B1 Apparatus for software initiated prefetch and method therefor 失效
标题翻译：软件启动预取装置及其方法
公开(公告)号：US06401192B1
公开(公告)日：2002-06-04
申请号：US09166435
申请日：1998-10-05
申请人： David Andrew Schroter , Michael Thomas Vaden
发明人： David Andrew Schroter , Michael Thomas Vaden
IPC分类号： G06F900
CPC分类号： G06F9/383 , G06F9/30047 , G06F9/3455 , G06F12/0862 , G06F2212/6028
摘要： A mechanism and method for software hint initiated prefetch is provided. The prefetch may be directed to a prefetch of data for loading into a data cache, instructions for entry into an instruction cache or for either, in an embodiment having a combined cache. In response to a software instruction in an instruction stream, a plurality of prefetch specification data values are loaded into a register having a plurality of entries corresponding thereto. Prefetch specification data values include the address of the first cache line to be prefetched, and the stride, or the incremental offset, of the address of subsequent lines to be prefetched. Prefetch requests are generated by a prefetch control state machine using the prefetch specification data values stored in the register. Prefetch requests are issued to a hierarchy of cache memory devices. If a cache hit occurs having the specified cache coherency, the prefetch is vitiated. Otherwise, the request is passed to system memory for retrieval of the requested cache line.
摘要翻译：提供了软件提示启动预取的机制和方法。预取可以被引导到用于加载到数据高速缓存中的数据的预取，用于进入指令高速缓存的指令，或者在具有组合高速缓存的实施例中。响应于指令流中的软件指令，将多个预取指定数据值加载到具有与其对应的多个条目的寄存器中。预取指定数据值包括要预取的第一个高速缓存行的地址以及要预取的后续行的地址的步幅或增量偏移量。预取请求由预取控制状态机使用寄存器中存储的预取指定数据值生成。预取请求被发布到高速缓存存储器设备的层次结构。如果发生具有指定高速缓存一致性的高速缓存命中，则预取将被破坏。否则，请求被传递到系统内存以检索所请求的高速缓存行。

4. 发明授权

US08024647B2 Method and system for checking rotate, shift and sign extension functions using a modulo function 失效
标题翻译：使用模函数检查旋转，移位和签名扩展函数的方法和系统
公开(公告)号：US08024647B2
公开(公告)日：2011-09-20
申请号：US12047525
申请日：2008-03-13
申请人： Fadi Y. Busaba , Lawrence Joseph Powell , Martin Stanley Schmookler , Michael Thomas Vaden , David Allan Webber
发明人： Fadi Y. Busaba , Lawrence Joseph Powell , Martin Stanley Schmookler , Michael Thomas Vaden , David Allan Webber
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： G06F11/2226
摘要： A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.
摘要翻译：公开了一种发现电路故障的方法。该方法包括通过在操作数上执行所选功能来产生所选功能的第一结果，其中所选功能采用掩码。一旦执行了该功能，就产生一个掩模的防范，并计算出锑的模数。计算所选函数的第一结果的模函数以获得第三结果。然后计算操作数的模以获得第四结果，然后对第二结果和第三结果执行第二函数以获得第五结果。响应于将第五结果与第四结果进行比较，传播信号以指示电路中的故障。

5. 发明申请

US20080162887A1 SYSTEM FOR GENERATING EFFECTIVE ADDRESS 有权
标题翻译：用于生成有效地址的系统
公开(公告)号：US20080162887A1
公开(公告)日：2008-07-03
申请号：US12048527
申请日：2008-03-14
申请人： RACHEL MARIE FLOOD , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein , Michael Thomas Vaden
发明人： RACHEL MARIE FLOOD , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein , Michael Thomas Vaden
IPC分类号： G06F9/30
CPC分类号： G06F9/355 , G06F9/30043 , G06F9/3816 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F12/1027
摘要： Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.
摘要翻译：用于在数据处理系统中生成有效地址的方法，系统和计算机程序产品。一种在数据处理系统中用于产生有效地址的方法包括通过计算有效地址的第一多个有效地址位来产生有效地址的第一部分，以及通过猜测有效地址产生有效地址的第二部分多个有效地址的有效地址位。通过智能地猜测形成有效地址的多个有效地址位，可以比在其中计算有效地址的所有有效地址位的系统中更快地生成有效地址并将其发送到转换单元。该方法和系统特别适用于在多线程环境中的基于CAM的有效地址转换设计中生成有效地址。

6. 发明授权

US07991816B2 Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units 失效
标题翻译：在结果总线上反转数据，准备高频执行单元下一个周期的指令
公开(公告)号：US07991816B2
公开(公告)日：2011-08-02
申请号：US12189797
申请日：2008-08-12
申请人： Brian William Curran , Ashutosh Goyal , Michael Thomas Vaden , David Allan Webber
发明人： Brian William Curran , Ashutosh Goyal , Michael Thomas Vaden , David Allan Webber
IPC分类号： G06F7/38
CPC分类号： G06F9/3001 , G06F9/3867
摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.
摘要翻译：一种通过将当前周期内要执行的操作的结果与来自指令解码逻辑的控制信号相反的操作算术逻辑单元（ALU）的方法，该指令解码逻辑指示稍后的操作将需要结果的补码，其中，结果在当前周期内反转。稍后的操作可以是紧跟在第一操作之后的减法操作。后续指令在当前周期之前进行解码，以控制ALU中的反转。 ALU包括加法器，旋转器和数据操作单元，其响应于反转控制信号在当前周期内反转结果。第二操作在随后的周期中减去结果，其中使能到加法器的进位控制信号，并且旋转器和数据操作单元被禁用。 ALU可以用在诸如定点单元的微处理器的执行单元中。

7. 发明申请

US20080162618A1 METHOD AND SYSTEM FOR CHECKING ROTATE, SHIFT AND SIGN EXTENSION FUNCTIONS USING A MODULO FUNCTION 失效
标题翻译：使用模块函数检查旋转，移位和符号扩展函数的方法和系统
公开(公告)号：US20080162618A1
公开(公告)日：2008-07-03
申请号：US12047525
申请日：2008-03-13
申请人： FADI Y. BUSABA , Lawrence Joseph Powell , Martin Stanley Schmookler , Michael Thomas Vaden , David Allan Webber
发明人： FADI Y. BUSABA , Lawrence Joseph Powell , Martin Stanley Schmookler , Michael Thomas Vaden , David Allan Webber
IPC分类号： G06F11/20
CPC分类号： G06F11/2226
摘要： A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.
摘要翻译：公开了一种发现电路故障的方法。该方法包括通过在操作数上执行所选功能来产生所选功能的第一结果，其中所选功能采用掩码。一旦执行了该功能，就产生一个掩模的防范，并计算出锑的模数。计算所选函数的第一结果的模函数以获得第三结果。然后计算操作数的模以获得第四结果，然后对第二结果和第三结果执行第二函数以获得第五结果。响应于将第五结果与第四结果进行比较，传播信号以指示电路中的故障。

8. 发明授权

US06914849B2 Method and apparatus for reducing power consumption in a memory array with dynamic word line driver/decoders 失效
标题翻译：用于通过动态字线驱动器/解码器降低存储器阵列功耗的方法和装置
公开(公告)号：US06914849B2
公开(公告)日：2005-07-05
申请号：US10687238
申请日：2003-10-16
申请人： Tai Anh Cao , Sam Gat-Shang Chu , Joseph J. McGill IV , Michael Thomas Vaden
发明人： Tai Anh Cao , Sam Gat-Shang Chu , Joseph J. McGill IV , Michael Thomas Vaden
IPC分类号： G11C7/10 , G11C7/22 , G11C8/08 , G11C8/18 , G11C8/00
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/22 , G11C7/225 , G11C8/08 , G11C8/18
摘要： A memory array includes a storage unit with a number of sections and decoders coupled to respective ones of the sections for decoding an N-bit address signal and responsively asserting a signal on one of the word lines selected by the address signal. Local clock buffers are coupled to respective ones of the decoders for receiving a clock signal and an address signal including M most-significant bits of the N-bit address signal and generating respective timing signals. The decoders receive the timing signal from their respective local clock buffers. Each decoder is operable to alternately precharge and evaluate the N-bit address signal responsive to phases of the timing signal. Each local clock buffer is operable, responsive to a state of the M bits of the address signal, for selecting between holding its timing signal in a deasserted state and enabling its timing signal to follow the clock signal.
摘要翻译：存储器阵列包括存储单元，其具有多个部分和解码器，所述部分和解码器耦合到相应的部分，用于对N位地址信号进行解码，并响应地确定由地址信号选择的一条字线上的信号。本地时钟缓冲器耦合到解码器中的相应解码器，用于接收时钟信号和包括N位地址信号的M个最高有效位的地址信号并产生相应的定时信号。解码器从其各自的本地时钟缓冲器接收定时信号。每个解码器可操作以响应于定时信号的相位交替地预充电和评估N位地址信号。每个本地时钟缓冲器可操作地响应于地址信号的M位的状态，用于在保持其定时信号处于无效状态并使其定时信号跟随时钟信号之间进行选择。

9. 发明授权

US5740399A Modified L1/L2 cache inclusion for aggressive prefetch 失效
标题翻译：修改的L1 / L2缓存包含用于积极预取
公开(公告)号：US5740399A
公开(公告)日：1998-04-14
申请号：US518348
申请日：1995-08-23
申请人： Michael John Mayfield , Trinh Huy Nguyen , Robert James Reese , Michael Thomas Vaden
发明人： Michael John Mayfield , Trinh Huy Nguyen , Robert James Reese , Michael Thomas Vaden
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0897
摘要： Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches.
摘要翻译：在实现L1和L2高速缓存以及流过滤器和缓冲器的数据处理系统内，以渐进方式执行高速缓存行的预取。在一种模式下，数据可能不被预取。在第二模式中，预取两条高速缓存线，其中一行被预取到L1高速缓存中，并且下一行被预取到流缓冲器中。在第三种模式下，一次预取多于两条的高速缓存行。在第三模式中，高速缓存行可以被预取到L1高速缓存，而不是L2缓存，导致L1和L2高速缓存之间不包括。

10. 发明申请

US20080301411A1 INVERTING DATA ON RESULT BUS TO PREPARE FOR INSTRUCTION IN THE NEXT CYCLE FOR HIGH FREQUENCY EXECUTION UNITS 失效
标题翻译：在高频执行单位的下一个周期中，将结果总线上的数据反转为准备指令
公开(公告)号：US20080301411A1
公开(公告)日：2008-12-04
申请号：US12189797
申请日：2008-08-12
申请人： Brian William Curran , Ashutosh Goyal , Michael Thomas Vaden , David Allan Webber
发明人： Brian William Curran , Ashutosh Goyal , Michael Thomas Vaden , David Allan Webber
IPC分类号： G06F9/302 , G06F9/312
CPC分类号： G06F9/3001 , G06F9/3867
摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.
摘要翻译：一种通过使来自指令解码逻辑的控制信号反应在当前周期期间执行的操作的结果来操作算术逻辑单元（ALU）的方法，其指示稍后的操作将需要结果的补码，其中，结果在当前周期内反转。稍后的操作可以是紧跟在第一操作之后的减法操作。后续指令在当前周期之前进行解码，以控制ALU中的反转。 ALU包括加法器，旋转器和数据操作单元，其响应于反转控制信号在当前周期内反转结果。第二操作在随后的周期中减去结果，其中使能到加法器的进位控制信号，并且旋转器和数据操作单元被禁用。 ALU可以用在诸如定点单元的微处理器的执行单元中。

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