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1. 发明授权

US08656332B2 Automated critical area allocation in a physical synthesized hierarchical design 失效
标题翻译：物理合成分层设计中的自动关键区域分配
公开(公告)号：US08656332B2
公开(公告)日：2014-02-18
申请号：US12394035
申请日：2009-02-26
申请人： Bruce M. Fleischer , David J. Geiger , Hung C. Ngo , Ruchir Puri , Haoxing Ren
发明人： Bruce M. Fleischer , David J. Geiger , Hung C. Ngo , Ruchir Puri , Haoxing Ren
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/84
摘要： A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other. Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages. This entire process is repeated until the optimization of the unit layout eventually converges.
摘要翻译：公开了一种用于在分级集成电路设计中有效执行时序关键单元级单元的自动布置的方法，计算机程序产品和数据处理系统。为了准备全局优化，在单元级别的整个单元，宏级单元被分配一个“放置力”，其用于限制宏级单元从其当前位置的移动。还定义每个宏元素的移动边界，以便将给定宏元素中的组件保持在彼此相对接近。然后，通过力导向布局算法，在设计的“扁平化”模型上执行单元设计的优化/放置，同时遵循移动边界。在这种“扁平化”优化之后，放置的“单位级”单元被建模为阻塞，并且宏元素被单独地优化，同时尊重阻塞的位置。重复这个整个过程，直到单元布局的优化最终收敛。

2. 发明授权

US4702592A Reticle assembly, system, and method for using the same 失效
标题翻译：标线组件，系统和使用方法
公开(公告)号：US4702592A
公开(公告)日：1987-10-27
申请号：US879890
申请日：1986-06-30
申请人： David J. Geiger , Sunny Lee , Eric Busch
发明人： David J. Geiger , Sunny Lee , Eric Busch
IPC分类号： G03F1/00 , G03F7/20 , G03B27/42
CPC分类号： G03F7/70066
摘要： A reticle assembly, exposure system, and method for exposing each of a plurality of levels of a single die or device dies of a semiconductor wafer to a pattern of radiation on a site-by-site exposure basis are disclosed. Radiation patterning means between a source of radiation and the semiconductor wafer pattern the radiation onto the semiconductor wafer and a stepping means incrementally moves the semiconductor wafer relative to the patterning means for exposing the device dies, one at a time, in succession. The patterning means includes a reticle assembly having a plurality of reticles arranged in a coplanar array with each reticle having a respective different die exposure pattern.
摘要翻译：公开了一种用于将半导体晶片的单个裸片或器件裸片的多个级别中的每一个暴露于基于现场曝光的辐射的掩模版组件，曝光系统和方法。在辐射源与半导体晶片之间的辐射图案化装置将半导体晶片上的辐射图案化，并且步进装置相对于图案形成装置递增地移动半导体晶片，用于一次一个接一个地暴露器件裸片。图案形成装置包括具有以共面阵列排列的多个标线片的掩模版组件，每个掩模具具有相应的不同的裸片曝光图案。

3. 发明申请

US20100218155A1 Automated Critical Area Allocation in a Physical Synthesized Hierarchical Design 失效
标题翻译：物理综合分层设计中的自动关键区域分配
公开(公告)号：US20100218155A1
公开(公告)日：2010-08-26
申请号：US12394035
申请日：2009-02-26
申请人： Bruce M. Fleischer , David J. Geiger , Hung C. Ngo , Ruchir Puri , Hoaxing Ren
发明人： Bruce M. Fleischer , David J. Geiger , Hung C. Ngo , Ruchir Puri , Hoaxing Ren
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/84
摘要： A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other.Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages. This entire process is repeated until the optimization of the unit layout eventually converges.
摘要翻译：公开了一种用于在分级集成电路设计中有效执行时序关键单元级单元的自动布置的方法，计算机程序产品和数据处理系统。为了准备全局优化，在单元级别的整个单元，宏级单元被分配一个“放置力”，其用于限制宏级单元从其当前位置的移动。还定义每个宏元素的移动边界，以便将给定宏元素中的组件保持在彼此相对接近。然后，通过力导向布局算法，在设计的“扁平化”模型上执行单元设计的优化/放置，同时遵循移动边界。在这种“扁平化”优化之后，放置的“单位级”单元被建模为阻塞，并且宏元素被单独地优化，同时尊重阻塞的位置。重复这个整个过程，直到单元布局的优化最终收敛。

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