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1. 发明授权

US07434080B1 Apparatus for interfacing and testing a phase locked loop in a field programmable gate array 有权
标题翻译：用于在现场可编程门阵列中连接和测试锁相环的装置
公开(公告)号：US07434080B1
公开(公告)日：2008-10-07
申请号：US10235245
申请日：2002-09-03
申请人： Wei-Min Kuo , Donald Y. Yu
发明人： Wei-Min Kuo , Donald Y. Yu
IPC分类号： G06F1/04
CPC分类号： G01R31/31725 , G01R31/3016
摘要： An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver modules and at least one buffer module. A phase locked loop selectively coupled to the RT modules, the RO modules, the TY modules, the receiver modules and at least one buffer module in the phase locked loop cluster.
摘要翻译：用于将现场可编程门阵列中的锁相环接口的装置。该装置包括锁相环集群。所述锁相环还包括多个RT模块，多个RO模块，至少一个TY模块，多个接收模块和至少一个缓冲模块。锁相环选择性地耦合到RT模块，RO模块，TY模块，接收器模块和锁相环集群中的至少一个缓冲模块。

2. 发明申请

US20080197905A1 FIELD-PROGRAMMABLE GATE ARRAY LOW VOLTAGE DIFFERENTIAL SIGNALING DRIVER UTILIZING TWO COMPLIMENTARY OUTPUT BUFFERS 有权
标题翻译：现场可编程门阵列使用两个紧凑输出缓冲器的低电压差分信号驱动器
公开(公告)号：US20080197905A1
公开(公告)日：2008-08-21
申请号：US12109487
申请日：2008-04-25
申请人： Donald Y. Yu , Wei-Min Kuo
发明人： Donald Y. Yu , Wei-Min Kuo
IPC分类号： H03H11/26
CPC分类号： H03K19/17744 , H03K19/017581
摘要： A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.
摘要翻译：低电压信号差分信令驱动器，包括耦合到延迟电路的第一输出线，第一多路复用器和第一输出缓冲器。第一输出线还耦合到反相器，第二多路复用器和第二输出缓冲器。

3. 发明授权

US07378867B1 Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers 失效
标题翻译：采用两个互补输出缓冲器的现场可编程门阵列低压差分信号驱动器
公开(公告)号：US07378867B1
公开(公告)日：2008-05-27
申请号：US11548199
申请日：2006-10-10
申请人： Donald Y. Yu , Wei-Min Kuo
发明人： Donald Y. Yu , Wei-Min Kuo
IPC分类号： H03K19/173
CPC分类号： H03K19/17744 , H03K19/017581
摘要： A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.
摘要翻译：低电压信号差分信令驱动器，包括耦合到延迟电路的第一输出线，第一多路复用器和第一输出缓冲器。第一输出线还耦合到反相器，第二多路复用器和第二输出缓冲器。

4. 发明授权

US06891394B1 Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers 有权
标题翻译：采用两个互补输出缓冲器的现场可编程门阵列低压差分信号驱动器
公开(公告)号：US06891394B1
公开(公告)日：2005-05-10
申请号：US10163096
申请日：2002-06-04
申请人： Donald Y. Yu , Wei-Min Kuo
发明人： Donald Y. Yu , Wei-Min Kuo
IPC分类号： H03K19/0175 , H03K19/177 , H03K19/173 , H03H11/26
CPC分类号： H03K19/17744 , H03K19/017581 , H03K19/17784
摘要： A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.
摘要翻译：低电压信号差分信令驱动器，包括耦合到延迟电路的第一输出线，第一多路复用器和第一输出缓冲器。第一输出线还耦合到反相器，第二多路复用器和第二输出缓冲器。

5. 发明授权

US06147908A Stable adjustable programming voltage scheme 失效
标题翻译：稳定的可编程电压方案
公开(公告)号：US06147908A
公开(公告)日：2000-11-14
申请号：US962860
申请日：1997-11-03
申请人： Khaldoon Abugharbieh , Donald Y. Yu , Roger J. Bettman
发明人： Khaldoon Abugharbieh , Donald Y. Yu , Roger J. Bettman
IPC分类号： G11C16/24 , G11C16/30 , G11C16/06
CPC分类号： G11C16/30 , G11C16/24
摘要： A nonvolatile memory circuit that includes a load circuit coupled to a band-gap reference circuit and a nonvolatile memory cell. The load line circuit is configured to provide a programming voltage to the nonvolatile memory cell. The programming voltage may be generated in response to the reference voltage generated by the band-gap reference circuit. The nonvolatile memory circuit may also include an amplifying circuit that amplifies the reference voltage of the band-gap circuit, and provides the amplified reference voltage to the load circuit. The nonvolatile memory circuit may further include a voltage trim circuit that trims the amplified reference voltage and provides the trimmed amplified reference voltage to the load circuit. The reference voltage, amplified reference voltage, and the trimmed amplified reference voltage may each output a stable voltage that is independent of variations in process parameters, operating temperatures, and supply voltages of the nonvolatile memory circuit.
摘要翻译：一种非易失性存储器电路，包括耦合到带隙基准电路和非易失性存储单元的负载电路。负载线电路被配置为向非易失性存储单元提供编程电压。编程电压可以响应于由带隙基准电路产生的参考电压而产生。非易失性存储器电路还可以包括放大电路，其放大带隙电路的参考电压，并将放大的参考电压提供给负载电路。非易失性存储器电路还可以包括修整放大的参考电压并将修整的放大参考电压提供给负载电路的电压调整电路。参考电压，放大参考电压和经修整的放大参考电压可以各自输出与非易失性存储器电路的工艺参数，工作温度和电源电压的变化无关的稳定电压。

6. 发明授权

US5867013A Startup circuit for band-gap reference circuit 失效
标题翻译：带隙参考电路启动电路
公开(公告)号：US5867013A
公开(公告)日：1999-02-02
申请号：US974436
申请日：1997-11-20
申请人： Donald Y. Yu
发明人： Donald Y. Yu
IPC分类号： G05F3/30 , G05F3/16
CPC分类号： G05F3/30 , Y10S323/901
摘要： A circuit includes a band-gap reference circuit and a start-up circuit coupled between an output and an input of the band-gap reference circuit. When the output of the band-gap reference circuit is below a start-up voltage threshold, the start-up circuit provides a first voltage at the input of the band-gap reference circuit which, in turn, causes the band-gap reference circuit to produce a desired voltage at the output. When the desired voltage has been reached, i.e., a voltage corresponding to the start-up voltage threshold, the start-up circuit turns off and does not interfere with the normal operation of the band-gap reference circuit. The start-up circuit may include first circuitry configured to produce a first voltage if a voltage signal at the output of the band-gap reference circuit is below the start-up voltage threshold. The start-up circuit may further include second circuitry coupled to the first circuitry and configured to produce a second voltage at the input of the band-gap reference circuit in response to the first voltage. The start-up voltage threshold may be a desirable output voltage, for example approximately 1.25 volts.
摘要翻译：电路包括耦合在带隙基准电路的输出端和输入端之间的带隙基准电路和启动电路。当带隙基准电路的输出低于启动电压阈值时，启动电路在带隙基准电路的输入端提供一个第一电压，这又导致带隙基准电路以在输出端产生所需的电压。当达到所需的电压，即对应于启动电压阈值的电压时，起动电路关断，并且不干扰带隙基准电路的正常工作。启动电路可以包括第一电路，其被配置为在带隙基准电路的输出处的电压信号低于启动电压阈值时产生第一电压。启动电路还可以包括耦合到第一电路并被配置为响应于第一电压在带隙参考电路的输入处产生第二电压的第二电路。启动电压阈值可以是期望的输出电压，例如大约1.25伏特。

7. 发明授权

US07774665B2 Apparatus for testing a phrase-locked loop in a boundary scan enabled device 有权
标题翻译：用于在边界扫描启用的设备中测试短语锁定环路的装置
公开(公告)号：US07774665B2
公开(公告)日：2010-08-10
申请号：US12198249
申请日：2008-08-26
申请人： Wei-Min Kuo , Donald Y. Yu
发明人： Wei-Min Kuo , Donald Y. Yu
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/3016
摘要： An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver modules and at least one buffer module. A phase locked loop selectively coupled to the RT modules, the RO modules, the TY modules, the receiver modules and at least one buffer module in the phase locked loop cluster.
摘要翻译：用于将现场可编程门阵列中的锁相环接口的装置。该装置包括锁相环集群。所述锁相环还包括多个RT模块，多个RO模块，至少一个TY模块，多个接收模块和至少一个缓冲模块。锁相环选择性地耦合到RT模块，RO模块，TY模块，接收器模块和锁相环集群中的至少一个缓冲模块。

8. 发明授权

US07545166B2 Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers 有权
标题翻译：采用两个互补输出缓冲器的现场可编程门阵列低压差分信号驱动器
公开(公告)号：US07545166B2
公开(公告)日：2009-06-09
申请号：US12109487
申请日：2008-04-25
申请人： Donald Y. Yu , Wei-Min Kuo
发明人： Donald Y. Yu , Wei-Min Kuo
IPC分类号： H03K19/173
CPC分类号： H03K19/17744 , H03K19/017581
摘要： A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.
摘要翻译：低电压信号差分信令驱动器，包括耦合到延迟电路的第一输出线，第一多路复用器和第一输出缓冲器。第一输出线还耦合到反相器，第二多路复用器和第二输出缓冲器。

9. 发明授权

US07119573B2 Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers 有权
公开(公告)号：US07119573B2
公开(公告)日：2006-10-10
申请号：US11123734
申请日：2005-05-05
申请人： Donald Y. Yu , Wei-Min Kuo
发明人： Donald Y. Yu , Wei-Min Kuo
IPC分类号： H03K19/173 , H03H11/26
CPC分类号： H03K19/17744 , H03K19/017581 , H03K19/17784
摘要： A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.

10. 发明申请

US20090045855A1 APPARATUS FOR INTERFACING AND TESTING A PHASE LOCKED LOOP IN A FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：在现场可编程门阵列中接口和测试相位锁定环的装置
公开(公告)号：US20090045855A1
公开(公告)日：2009-02-19
申请号：US12198249
申请日：2008-08-26
申请人： Wei-Min Kuo , Donald Y. Yu
发明人： Wei-Min Kuo , Donald Y. Yu
IPC分类号： H03L7/07 , G01R31/02
CPC分类号： G01R31/31725 , G01R31/3016
摘要： An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver modules and at least one buffer module. A phase locked loop selectively coupled to the RT modules, the RO modules, the TY modules, the receiver modules and at least one buffer module in the phase locked loop cluster.
摘要翻译：用于将现场可编程门阵列中的锁相环接口的装置。该装置包括锁相环集群。所述锁相环还包括多个RT模块，多个RO模块，至少一个TY模块，多个接收模块和至少一个缓冲模块。锁相环选择性地耦合到RT模块，RO模块，TY模块，接收器模块和锁相环集群中的至少一个缓冲模块。

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