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1. 发明授权

US07785985B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07785985B2
公开(公告)日：2010-08-31
申请号：US12133772
申请日：2008-06-05
申请人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
发明人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823456 , H01L27/0921 , H01L27/105
摘要： Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.
摘要翻译：可以减少热电子穿透（HEIP）和/或改善器件的工作特性的半导体器件的制造方法包括根据器件隔离层隔离的晶体管的特性选择性地在器件隔离层中形成氧氮化物层。所述方法包括在衬底上形成第一沟槽和第二沟槽，在第一沟槽和第二沟槽的表面上形成氧化物层，通过使用等离子体离子浸没注入（PIII）在第二沟槽上选择性地形成氧氮化物层，并形成在第一沟槽和第二沟槽中的掩埋绝缘层。掩埋绝缘层可以被平坦化以在第一沟槽中形成第一器件隔离层，在第二沟槽中形成第二器件隔离层。

2. 发明申请

US20090311846A1 METHOD OF FORMING SHALLOW TRENCH ISOLATION REGIONS IN DEVICES WITH NMOS AND PMOS REGIONS 失效
标题翻译：在具有NMOS和PMOS区域的器件中形成低温分离区的方法
公开(公告)号：US20090311846A1
公开(公告)日：2009-12-17
申请号：US12466178
申请日：2009-05-14
申请人： Dong-Woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
发明人： Dong-Woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/10894 , H01L27/11546
摘要： A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.
摘要翻译：在其中限定了单元区域，PMOS区域和NMOS区域的半导体衬底上形成掩模图案。在单元区域，PMOS区域和NMOS区域中形成沟槽。在沟槽中形成侧壁氧化物层和保护层，并且去除PMOS区域中的保护层的一部分。在衬底上形成第一器件隔离绝缘层，填充沟槽。去除第一器件隔离绝缘层的部分以露出掩模图案和单元区域和NMOS区域的沟槽，并且在PMOS区域的沟槽中留下第一器件隔离绝缘层的一部分。衬垫形成在PMOS区域的沟槽中的第一器件隔离区域的部分上，并且与衬底区域和NMOS区域中的沟槽的侧壁一致。在衬底上形成第二器件隔离绝缘层，填充单元区域和NMOS区域中的沟槽。去除第二器件隔离绝缘层的部分以暴露掩模图案并且将第二器件隔离绝缘层的部分留在单元区域和NMOS区域的沟槽中。

3. 发明申请

US20100240207A1 METHODS OF MANUFACTURING CHARGE TRAP TYPE MEMORY DEVICES 有权
标题翻译：制造电荷陷阱型存储器件的方法
公开(公告)号：US20100240207A1
公开(公告)日：2010-09-23
申请号：US12726014
申请日：2010-03-17
申请人： Young-Geun Park , Jae-Young Ahn , Jun-Kyu Yang , Dong-Woon Shin
发明人： Young-Geun Park , Jae-Young Ahn , Jun-Kyu Yang , Dong-Woon Shin
IPC分类号： H01L21/8246
CPC分类号： H01L27/11568 , H01L27/11521
摘要： Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.
摘要翻译：电荷阱型存储器件的制造可以包括在衬底上形成隧道绝缘层。电荷捕获层可以形成在隧道绝缘层上。可以在电荷捕获层上形成阻挡层。栅电极可以形成在阻挡层上并被沟槽分隔。与沟槽对准的电荷俘获层的一部分可以通过各向异性氧化工艺转变成具有垂直侧面轮廓的电荷阻挡图案。

4. 发明申请

US20100210116A1 METHODS OF FORMING VAPOR THIN FILMS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME 审中-公开
标题翻译：形成蒸气薄膜的方法和包括其的半导体集成电路装置
公开(公告)号：US20100210116A1
公开(公告)日：2010-08-19
申请号：US12704299
申请日：2010-02-11
申请人： Jae-Young AHN , Ki-Hyun Hwang , Young-Geun Park , Jun-Kyu Yang , Byong-Sun Ju , Dong-Woon Shin
发明人： Jae-Young AHN , Ki-Hyun Hwang , Young-Geun Park , Jun-Kyu Yang , Byong-Sun Ju , Dong-Woon Shin
IPC分类号： H01L21/461
CPC分类号： H01L21/76837 , C23C16/045 , C23C16/45542 , H01L21/02164 , H01L21/02211 , H01L21/02219 , H01L21/02274 , H01L21/0228
摘要： A method of forming a vapor thin film is provided, which includes loading a substrate into a chamber, adsorbing a source gas on the substrate by supplying the source gas into the chamber, and forming the thin film on the substrate by supplying a reaction gas into the chamber, wherein the forming of the thin film on the substrate is proceeded under an electric field formed in one direction on the substrate by applying a bias to the substrate.
摘要翻译：提供一种形成蒸气薄膜的方法，其包括将基板装载到室中，通过将源气体供应到室中来将源气体吸附在基板上，并通过将反应气体供应到基板上而形成薄膜其中，通过向衬底施加偏压，在衬底上的薄膜的形成在基板上沿一个方向形成的电场上进行。

5. 发明申请

US20100117141A1 Memory cell transistors having limited charge spreading, non-volatile memory devices including such transistors, and methods of formation thereof 审中-公开
标题翻译：具有有限电荷扩展的存储单元晶体管，包括这种晶体管的非易失性存储器件及其形成方法
公开(公告)号：US20100117141A1
公开(公告)日：2010-05-13
申请号：US12590641
申请日：2009-11-12
申请人： Dong-woon Shin , Young-Kun Park , Jun-gyu Yang , Jae-young Ahn , Ki-hyun Hwang , Si-young Choi
发明人： Dong-woon Shin , Young-Kun Park , Jun-gyu Yang , Jae-young Ahn , Ki-hyun Hwang , Si-young Choi
IPC分类号： H01L27/105 , H01L29/792
CPC分类号： H01L27/11582 , G11C5/02 , G11C16/0475 , G11C16/0483 , H01L27/11568 , H01L27/11578 , H01L29/40117 , H01L29/4234 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： In one aspect, a transistor comprises: a substrate body; a tunnel oxide layer on the body; a charge trapping layer on the tunnel oxide layer; a blocking layer on the charge trapping layer; a control gate on the blocking layer, the control gate having first and second sidewalls, the first and second sidewalls being spaced apart from each other by a first distance; and charge confinement features on the body, the charge confinement features being spaced apart from each other by a second distance that is greater than or substantially equal to the first distance, the charge confinement features suppressing or preventing migration of charge present in the charge trapping layer.
摘要翻译：一方面，晶体管包括：衬底本体; 身体上的隧道氧化层; 隧道氧化层上的电荷捕获层; 电荷俘获层上的阻挡层; 所述阻挡层上的控制栅极，所述控制栅极具有第一和第二侧壁，所述第一和第二侧壁彼此隔开第一距离; 并且在身体上充电限制特征，所述电荷限制特征彼此间隔开大于或基本上等于所述第一距离的第二距离，所述电荷限制特征抑制或防止存在于所述电荷俘获层中的电荷的迁移。

6. 发明授权

US08097531B2 Methods of manufacturing charge trap type memory devices 有权
标题翻译：制造电荷阱型存储器件的方法
公开(公告)号：US08097531B2
公开(公告)日：2012-01-17
申请号：US12726014
申请日：2010-03-17
申请人： Young-Geun Park , Jae-Young Ahn , Jun-Kyu Yang , Dong-Woon Shin
发明人： Young-Geun Park , Jae-Young Ahn , Jun-Kyu Yang , Dong-Woon Shin
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11568 , H01L27/11521
摘要： Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.
摘要翻译：电荷阱型存储器件的制造可以包括在衬底上形成隧道绝缘层。电荷捕获层可以形成在隧道绝缘层上。可以在电荷捕获层上形成阻挡层。栅电极可以形成在阻挡层上并被沟槽分隔。与沟槽对准的电荷俘获层的一部分可以通过各向异性氧化工艺转变成具有垂直侧面轮廓的电荷阻挡图案。

7. 发明申请

US20090203189A1 METHODS OF MANUFACTURING TRENCH ISOLATION STRUCTURES USING SELECTIVE PLASMA ION IMMERSION IMPLANTATION AND DEPOSITION (PIIID) 有权
标题翻译：使用选择性等离子体离子注入和沉积（PIIID）制造TRENCH隔离结构的方法
公开(公告)号：US20090203189A1
公开(公告)日：2009-08-13
申请号：US12134760
申请日：2008-06-06
申请人： Dong-woon Shin , Tai-su Park , Si-Young Choi , Soo-Jin Hong , Mi-Jin Kim
发明人： Dong-woon Shin , Tai-su Park , Si-Young Choi , Soo-Jin Hong , Mi-Jin Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823456 , H01L27/0921 , H01L27/105
摘要： A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.
摘要翻译：通过在衬底中形成沟槽并且在衬底中的沟槽的子集上选择性地执行等离子体离子注入植入和沉积（PIIID）来制造半导体器件。 PIIID可以仅在衬底中的至少一个沟槽的表面的一部分上进行。半导体器件可以包括其中具有第一，第二和第三沟槽的半导体衬底以及不对第一沟槽进行线条化的氧化物衬层，其不线性化第二沟槽并且部分地对第三沟槽进行排列。

8. 发明申请

US20090203188A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090203188A1
公开(公告)日：2009-08-13
申请号：US12133772
申请日：2008-06-05
申请人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
发明人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823456 , H01L27/0921 , H01L27/105
摘要： Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.
摘要翻译：可以减少热电子穿透（HEIP）和/或改善器件的工作特性的半导体器件的制造方法包括根据器件隔离层隔离的晶体管的特性选择性地在器件隔离层中形成氧氮化物层。所述方法包括在衬底上形成第一沟槽和第二沟槽，在第一沟槽和第二沟槽的表面上形成氧化物层，通过使用等离子体离子浸没注入（PIII）在第二沟槽上选择性地形成氧氮化物层，并形成在第一沟槽和第二沟槽中的掩埋绝缘层。掩埋绝缘层可以被平坦化以在第一沟槽中形成第一器件隔离层，在第二沟槽中形成第二器件隔离层。

9. 发明授权

US07871897B2 Method of forming shallow trench isolation regions in devices with NMOS and PMOS regions 失效
标题翻译：在具有NMOS和PMOS区域的器件中形成浅沟槽隔离区的方法
公开(公告)号：US07871897B2
公开(公告)日：2011-01-18
申请号：US12466178
申请日：2009-05-14
申请人： Dong-woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
发明人： Dong-woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/10894 , H01L27/11546
摘要： A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.
摘要翻译：在其中限定了单元区域，PMOS区域和NMOS区域的半导体衬底上形成掩模图案。在单元区域，PMOS区域和NMOS区域中形成沟槽。在沟槽中形成侧壁氧化物层和保护层，并且去除PMOS区域中的保护层的一部分。在衬底上形成第一器件隔离绝缘层，填充沟槽。去除第一器件隔离绝缘层的部分以露出掩模图案和单元区域和NMOS区域的沟槽，并且在PMOS区域的沟槽中留下第一器件隔离绝缘层的一部分。衬垫形成在PMOS区域的沟槽中的第一器件隔离区域的部分上，并且与衬底区域和NMOS区域中的沟槽的侧壁一致。在衬底上形成第二器件隔离绝缘层，填充单元区域和NMOS区域中的沟槽。去除第二器件隔离绝缘层的部分以暴露掩模图案并且将第二器件隔离绝缘层的部分留在单元区域和NMOS区域的沟槽中。

10. 发明授权

US07807543B2 Methods of manufacturing trench isolation structures using selective plasma ion immersion implantation and deposition (PIIID) 有权
标题翻译：使用选择性等离子体离子浸入和沉积（PIIID）制造沟槽隔离结构的方法
公开(公告)号：US07807543B2
公开(公告)日：2010-10-05
申请号：US12134760
申请日：2008-06-06
申请人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
发明人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823456 , H01L27/0921 , H01L27/105
摘要： A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.
摘要翻译：通过在衬底中形成沟槽并且在衬底中的沟槽的子集上选择性地执行等离子体离子注入植入和沉积（PIIID）来制造半导体器件。 PIIID可以仅在衬底中的至少一个沟槽的表面的一部分上进行。半导体器件可以包括其中具有第一，第二和第三沟槽的半导体衬底以及不对第一沟槽进行线条化的氧化物衬层，其不线性化第二沟槽并且部分地对第三沟槽进行排列。

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