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1. 发明申请

US20100240207A1 METHODS OF MANUFACTURING CHARGE TRAP TYPE MEMORY DEVICES 有权
标题翻译：制造电荷陷阱型存储器件的方法
公开(公告)号：US20100240207A1
公开(公告)日：2010-09-23
申请号：US12726014
申请日：2010-03-17
申请人： Young-Geun Park , Jae-Young Ahn , Jun-Kyu Yang , Dong-Woon Shin
发明人： Young-Geun Park , Jae-Young Ahn , Jun-Kyu Yang , Dong-Woon Shin
IPC分类号： H01L21/8246
CPC分类号： H01L27/11568 , H01L27/11521
摘要： Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.
摘要翻译：电荷阱型存储器件的制造可以包括在衬底上形成隧道绝缘层。电荷捕获层可以形成在隧道绝缘层上。可以在电荷捕获层上形成阻挡层。栅电极可以形成在阻挡层上并被沟槽分隔。与沟槽对准的电荷俘获层的一部分可以通过各向异性氧化工艺转变成具有垂直侧面轮廓的电荷阻挡图案。

2. 发明申请

US20100210116A1 METHODS OF FORMING VAPOR THIN FILMS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME 审中-公开
标题翻译：形成蒸气薄膜的方法和包括其的半导体集成电路装置
公开(公告)号：US20100210116A1
公开(公告)日：2010-08-19
申请号：US12704299
申请日：2010-02-11
申请人： Jae-Young AHN , Ki-Hyun Hwang , Young-Geun Park , Jun-Kyu Yang , Byong-Sun Ju , Dong-Woon Shin
发明人： Jae-Young AHN , Ki-Hyun Hwang , Young-Geun Park , Jun-Kyu Yang , Byong-Sun Ju , Dong-Woon Shin
IPC分类号： H01L21/461
CPC分类号： H01L21/76837 , C23C16/045 , C23C16/45542 , H01L21/02164 , H01L21/02211 , H01L21/02219 , H01L21/02274 , H01L21/0228
摘要： A method of forming a vapor thin film is provided, which includes loading a substrate into a chamber, adsorbing a source gas on the substrate by supplying the source gas into the chamber, and forming the thin film on the substrate by supplying a reaction gas into the chamber, wherein the forming of the thin film on the substrate is proceeded under an electric field formed in one direction on the substrate by applying a bias to the substrate.
摘要翻译：提供一种形成蒸气薄膜的方法，其包括将基板装载到室中，通过将源气体供应到室中来将源气体吸附在基板上，并通过将反应气体供应到基板上而形成薄膜其中，通过向衬底施加偏压，在衬底上的薄膜的形成在基板上沿一个方向形成的电场上进行。

3. 发明授权

US08097531B2 Methods of manufacturing charge trap type memory devices 有权
标题翻译：制造电荷阱型存储器件的方法
公开(公告)号：US08097531B2
公开(公告)日：2012-01-17
申请号：US12726014
申请日：2010-03-17
申请人： Young-Geun Park , Jae-Young Ahn , Jun-Kyu Yang , Dong-Woon Shin
发明人： Young-Geun Park , Jae-Young Ahn , Jun-Kyu Yang , Dong-Woon Shin
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11568 , H01L27/11521
摘要： Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.
摘要翻译：电荷阱型存储器件的制造可以包括在衬底上形成隧道绝缘层。电荷捕获层可以形成在隧道绝缘层上。可以在电荷捕获层上形成阻挡层。栅电极可以形成在阻挡层上并被沟槽分隔。与沟槽对准的电荷俘获层的一部分可以通过各向异性氧化工艺转变成具有垂直侧面轮廓的电荷阻挡图案。

4. 发明授权

US07442981B2 Capacitor of semiconductor device and method of fabricating the same 有权
标题翻译：半导体器件的电容器及其制造方法
公开(公告)号：US07442981B2
公开(公告)日：2008-10-28
申请号：US11316487
申请日：2005-12-21
申请人： Gab-Jin Nam , Young-Sun Kim , Cha-Young Yoo , Jong-Cheol Lee , Jin-Tae Noh , Jae-Young Ahn , Young-Geun Park , Jae-Hyoung Choi , Jae-Hyun Yeo
发明人： Gab-Jin Nam , Young-Sun Kim , Cha-Young Yoo , Jong-Cheol Lee , Jin-Tae Noh , Jae-Young Ahn , Young-Geun Park , Jae-Hyoung Choi , Jae-Hyun Yeo
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/75 , H01L27/10817 , H01L27/10852 , H01L28/91
摘要： Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.
摘要翻译：提供一种半导体器件的电容器及其制造方法。在一个实施例中，电容器包括形成在半导体衬底上的下电极; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。上电极包括依次堆叠的第一导电层，第二导电层和第三导电层。第一导电层包括金属层，导电金属氧化物层，导电金属氮化物层或导电金属氮氧化物层。第二导电层包括掺杂多晶硅锗层。第三导电层包括具有比第二导电层的电阻低的电阻的材料。

5. 发明申请

US20060186452A1 Capacitor of semiconductor device and method of fabricating the same 有权
标题翻译：半导体器件的电容器及其制造方法
公开(公告)号：US20060186452A1
公开(公告)日：2006-08-24
申请号：US11316487
申请日：2005-12-21
申请人： Gab-Jin Nam , Young-Sun Kim , Cha-Young Yoo , Jong-Cheol Lee , Jin-Tae Noh , Jae-Young Ahn , Young-Geun Park , Jae-Hyoung Choi , Jae-Hyun Yeo
发明人： Gab-Jin Nam , Young-Sun Kim , Cha-Young Yoo , Jong-Cheol Lee , Jin-Tae Noh , Jae-Young Ahn , Young-Geun Park , Jae-Hyoung Choi , Jae-Hyun Yeo
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/75 , H01L27/10817 , H01L27/10852 , H01L28/91
摘要： Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.
摘要翻译：提供一种半导体器件的电容器及其制造方法。在一个实施例中，电容器包括形成在半导体衬底上的下电极; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。上电极包括依次堆叠的第一导电层，第二导电层和第三导电层。第一导电层包括金属层，导电金属氧化物层，导电金属氮化物层或导电金属氮氧化物层。第二导电层包括掺杂多晶硅锗层。第三导电层包括具有比第二导电层的电阻低的电阻的材料。

6. 发明授权

US08497142B2 Methods of forming conductive layer patterns using gas phase cleaning process and methods of manufacturing semiconductor devices 有权
标题翻译：使用气相清洗工艺形成导电层图案的方法和制造半导体器件的方法
公开(公告)号：US08497142B2
公开(公告)日：2013-07-30
申请号：US13102218
申请日：2011-05-06
申请人： Jun-Kyu Yang , Young-Geun Park , Ki-Hyun Hwang , Han-Mei Choi , Dong-Chul Yoo
发明人： Jun-Kyu Yang , Young-Geun Park , Ki-Hyun Hwang , Han-Mei Choi , Dong-Chul Yoo
IPC分类号： H01L21/66 , H01L21/44
CPC分类号： H01L21/02071 , H01L21/02074 , H01L21/28282 , H01L21/321 , H01L21/76834 , H01L22/12 , H01L22/20 , H01L27/1052 , H01L27/10817 , H01L27/10873 , H01L27/11573 , H01L27/11578 , H01L27/11582 , H01L27/2436 , H01L28/40 , H01L29/66833 , H01L29/7926 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current.
摘要翻译：形成导电图案的方法包括在基板上形成包括金属元素的导电层。导电层被部分地蚀刻以产生包括金属元素的氧化物的残渣并且形成多个单独形成的导电层图案。清洁气体流入包括导电层图案的基板上。蒸发金属化合物以除去残留物中所含的金属元素，并通过一部分清洁气体和氧气的反应在导电层图案和基板的表面部分上形成绝缘界面层。可以从导电层图案中除去残留物以抑制漏电流的产生。

7. 发明申请

US20110165750A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING STRUCTURES 审中-公开
标题翻译：制造包括结构在内的半导体器件的方法
公开(公告)号：US20110165750A1
公开(公告)日：2011-07-07
申请号：US12984940
申请日：2011-01-05
申请人： Jun-Kyu Yang , Young-Geun Park , Ki-Hyun Hwang , Han-Mei Choi , Chan-Jin Park
发明人： Jun-Kyu Yang , Young-Geun Park , Ki-Hyun Hwang , Han-Mei Choi , Chan-Jin Park
IPC分类号： H01L21/336
CPC分类号： H01L21/7682 , H01L21/02164 , H01L21/02266 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： In methods of manufacturing a semiconductor device, a plurality of gate structures spaced apart from each other and oxide layer patterns. A sputtering process using the oxide layer patterns as a sputtering target to connect the oxide layer patterns on the adjacent gate structures to each other is performed, so that a gap is formed between the gate structures. A volume of the gap is formed uniformly to have desired volume by controlling a thickness of the oxide layer patterns.
摘要翻译：在制造半导体器件的方法中，多个彼此间隔开的栅极结构和氧化物层图案。执行使用氧化物层图案作为溅射靶的溅射工艺来将相邻栅极结构上的氧化物层图案彼此连接，使得在栅极结构之间形成间隙。通过控制氧化物层图案的厚度，使间隙的体积均匀地形成为具有期望的体积。

8. 发明申请

US20100052041A1 Nonvolatile Memory Devices Having Charge-Trap Layers Therein with Relatively High Election Affinity 审中-公开
标题翻译：具有电荷陷阱层的非易失性存储器件具有较高的选择亲和度
公开(公告)号：US20100052041A1
公开(公告)日：2010-03-04
申请号：US12550958
申请日：2009-08-31
申请人： Junkyu Yang , Young-Geun Park , Chunhyung Chung , EunSok Choi , Seon-Ho Jo , Hanmei Choi , Young-Sun Kim
发明人： Junkyu Yang , Young-Geun Park , Chunhyung Chung , EunSok Choi , Seon-Ho Jo , Hanmei Choi , Young-Sun Kim
IPC分类号： H01L29/792
CPC分类号： H01L29/4234 , H01L29/40117 , H01L29/513 , H01L29/517 , H01L29/792
摘要： Provided is a nonvolatile memory device. The nonvolatile memory device may include a tunnel insulating layer on a semiconductor substrate; a charge trap layer disposed on the tunnel insulating layer and having an electron affinity greater than a silicon nitride layer; a barrier insulating layer on the charge trap layer; a blocking insulating layer on the barrier insulating layer; and a gate electrode on the blocking insulating layer. An electron affinity of the barrier insulating layer is smaller than an electron affinity of the blocking insulating layer.
摘要翻译：提供了一种非易失性存储器件。非易失性存储器件可以包括在半导体衬底上的隧道绝缘层; 电荷陷阱层，其设置在所述隧道绝缘层上并且具有大于氮化硅层的电子亲和力; 电荷陷阱层上的阻挡绝缘层; 阻挡绝缘层上的阻挡绝缘层; 以及在所述阻挡绝缘层上的栅电极。阻挡绝缘层的电子亲和力小于阻挡绝缘层的电子亲和力。

9. 发明授权

US07517750B2 Flash memory devices having multilayered inter-gate dielectric layers including metal oxide layers and methods of manufacturing the same 失效
标题翻译：具有包括金属氧化物层的多层栅极间电介质层的闪存器件及其制造方法
公开(公告)号：US07517750B2
公开(公告)日：2009-04-14
申请号：US11383102
申请日：2006-05-12
申请人： Han-Mei Choi , Young-Geun Park , Seung-Hwan Lee , Young-Sun Kim
发明人： Han-Mei Choi , Young-Geun Park , Seung-Hwan Lee , Young-Sun Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： Embodiments of the present invention provide methods of manufacturing memory devices including forming floating gate patterns on a semiconductor substrate having active regions thereon, wherein the floating gate patterns cover the active regions and are spaced apart from the active regions; forming an inter-gate dielectric layer on the semiconductor substrate having the floating gate patterns by alternately stacking a zirconium oxide layer and an aluminum oxide layer at least once, wherein the inter-gate dielectric layer is formed by a deposition process using O3 gas as a reactive gas; forming a control gate layer on the inter-gate dielectric layer; and forming a control gate, an inter-gate dielectric layer pattern and a floating gate by sequentially patterning the control gate layer, the inter-gate dielectric layer and the floating gate pattern, wherein the inter-gate dielectric layer pattern and the control gate are sequentially stacked across the active regions, and the floating gate is formed between the active regions and the inter-gate dielectric layer pattern Memory devices, such as flash memory devices are also provided.
摘要翻译：本发明的实施例提供了制造存储器件的方法，包括在其上具有有源区的半导体衬底上形成浮置栅极图案，其中浮置栅极图案覆盖有源区并与有源区间隔开; 通过将氧化锆层和氧化铝层交替层叠至少一次来形成具有浮置栅极图案的半导体衬底上的栅极间电介质层，其中栅极间电介质层通过使用O 3气体作为反应气体在所述栅极间电介质层上形成控制栅极层; 以及通过对控制栅极层，栅极间电介质层和浮置栅极图案顺序构图来形成控制栅极，栅极间电介质层图案和浮置栅极，其中栅极间电介质层图案和控制栅极是顺序堆叠在有源区上，并且在有源区之间形成浮栅，并且还提供诸如闪存器件的栅极间电介质层图案存储器件。

10. 发明申请

US20070032013A1 METHODS OF FORMING A METAL OXIDE LAYER INCLUDING ZIRCONIUM OXIDE AND METHODS OF FORMING A CAPACITOR FOR SEMICONDUCTOR DEVICES INCLUDING THE SAME 审中-公开
标题翻译：形成包含氧化锆的金属氧化物层的方法和形成包括其的半导体器件的电容器的方法
公开(公告)号：US20070032013A1
公开(公告)日：2007-02-08
申请号：US11462405
申请日：2006-08-04
申请人： Kyoung-Ryul Yoon , Young-Geun Park , Ki-Vin Im , Jae-Hyun Yeo , Eun-Ae Chung , Young-Sun Kim
发明人： Kyoung-Ryul Yoon , Young-Geun Park , Ki-Vin Im , Jae-Hyun Yeo , Eun-Ae Chung , Young-Sun Kim
IPC分类号： H01L21/8242
CPC分类号： H01L21/02189 , C23C16/405 , C23C16/56 , H01L21/02266 , H01L21/02271 , H01L21/0228 , H01L21/0234 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L21/31641 , H01L27/10852 , H01L27/11507 , H01L28/40 , H01L29/40114 , H01L29/40117 , H01L29/517 , H01L29/7833
摘要： The present invention provides methods of forming a metal oxide layer and methods of forming a capacitor including the same. The methods of forming the metal oxide include forming a thin layer including a metal oxide, such as zirconium oxide, on a substrate and performing a post-treatment on the thin layer at a temperature at which oxygen present in the metal oxide is hindered from being diffused in the thin layer. Consequently, reduced amounts of byproducts are present on the boundary surface of the thin layer and the substrate thereby improving electrical characteristics of the thin layer.
摘要翻译：本发明提供了形成金属氧化物层的方法和形成包括该金属氧化物层的电容器的方法。形成金属氧化物的方法包括在衬底上形成包含氧化锆等金属氧化物的薄层，并在金属氧化物中存在的氧被阻碍的温度下在薄层上进行后处理扩散在薄层。因此，在薄层和基板的边界表面上存在减少量的副产物，从而改善薄层的电特性。

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