专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08435864B2 Process for single and multiple level metal-insulator-metal integration with a single mask 有权
标题翻译：单层和多层金属绝缘体金属与单一掩模集成的工艺
公开(公告)号：US08435864B2
公开(公告)日：2013-05-07
申请号：US13432440
申请日：2012-03-28
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/32136 , H01L28/75
摘要： A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
摘要翻译：提供一种制造MIM电容器的方法。该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。上板被切下，使得上板的边缘位于掩模下方。使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

2. 发明申请

US20120292741A1 INTERCONNECT STRUCTURES AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT 有权
标题翻译：无线电集成电路的互连结构和设计结构
公开(公告)号：US20120292741A1
公开(公告)日：2012-11-22
申请号：US13560446
申请日：2012-07-27
申请人： Timothy Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
发明人： Timothy Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
IPC分类号： H01L23/522 , G06F17/50
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L27/016 , H01L28/20 , H01L28/40
摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.
摘要翻译：包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计，制造或测试诸如射频集成电路的集成电路。电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。

3. 发明申请

US20120133022A1 METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE 有权
标题翻译：无平面化和相关半导体器件制造被动元件的方法
公开(公告)号：US20120133022A1
公开(公告)日：2012-05-31
申请号：US13359634
申请日：2012-01-27
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L29/92 , H01L29/8605
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

4. 发明授权

US08159040B2 Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor 有权
标题翻译：金属栅极集成结构和方法，包括金属保险丝，反熔丝和/或电阻
公开(公告)号：US08159040B2
公开(公告)日：2012-04-17
申请号：US12119526
申请日：2008-05-13
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
IPC分类号： H01L29/00
CPC分类号： H01L27/0629 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.
摘要翻译：半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料栅电极。

5. 发明授权

US08129234B2 Method of forming bipolar transistor integrated with metal gate CMOS devices 失效
标题翻译：与金属栅极CMOS器件集成的双极晶体管的形成方法
公开(公告)号：US08129234B2
公开(公告)日：2012-03-06
申请号：US12556205
申请日：2009-09-09
申请人： Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
发明人： Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
IPC分类号： H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
摘要翻译：形成高k栅极电介质层和金属栅极层，并图案化以暴露双极结型晶体管区域中的半导体表面，同时覆盖CMOS区域。一次性材料部分形成在双极结型晶体管区域中暴露的半导体表面的一部分上。沉积半导体层和电介质层，以形成包括CMOS区域中的半导体部分和介电栅极盖的栅极堆叠，以及在双极结型晶体管区域中的一次性材料部分上的包含台面的空腔。选择性地去除一次性材料部分，并且包括外延部分和多晶部分的基层填充通过去除一次性材料部分而形成的空腔。通过选择性外延形成的发射体填充台面中的空腔。

6. 发明授权

US08120143B2 Integrated circuit comb capacitor 有权
标题翻译：集成电路梳状电容
公开(公告)号：US08120143B2
公开(公告)日：2012-02-21
申请号：US12034728
申请日：2008-02-21
申请人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
发明人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L28/87 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.
摘要翻译：本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

7. 发明授权

US08093679B2 Integrated BEOL thin film resistor 有权
标题翻译：集成BEOL薄膜电阻
公开(公告)号：US08093679B2
公开(公告)日：2012-01-10
申请号：US13023579
申请日：2011-02-09
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
IPC分类号： H01L29/00 , H01L27/10 , H01L29/74 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.
摘要翻译：在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

8. 发明授权

US08039354B2 Passive components in the back end of integrated circuits 有权
标题翻译：集成电路后端的被动元件
公开(公告)号：US08039354B2
公开(公告)日：2011-10-18
申请号：US12849086
申请日：2010-08-03
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
IPC分类号： H01L21/02
CPC分类号： H01L23/5228 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
摘要翻译：通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

9. 发明授权

US07902629B2 Integrated BEOL thin film resistor 有权
标题翻译：集成BEOL薄膜电阻
公开(公告)号：US07902629B2
公开(公告)日：2011-03-08
申请号：US12271942
申请日：2008-11-17
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
IPC分类号： H01L29/00 , H01L27/10 , H01L29/74 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.
摘要翻译：在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

10. 发明申请

US20100237467A1 Interconnect Structures, Methods for Fabricating Interconnect Structures, and Design Structures for a Radiofrequency Integrated Circuit 有权
标题翻译：互连结构，制造互连结构的方法和射频集成电路的设计结构
公开(公告)号：US20100237467A1
公开(公告)日：2010-09-23
申请号：US12634742
申请日：2009-12-10
申请人： Timothy Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
发明人： Timothy Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
IPC分类号： H01L29/86 , G06F17/50 , H01L21/768
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L27/016 , H01L28/20 , H01L28/40
摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.
摘要翻译：包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计，制造或测试诸如射频集成电路的集成电路。电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式